CS47L35 datasheet(194/300 Pages) CIRRUS

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194

DS1085F3

CS47L35

4.16 Clocking and Sample Rates

In AIF Slave Modes, it is important to ensure that SYSCLK is synchronized with the associated external LRCLK. This can

be achieved by selecting an MCLK input that is derived from the same reference as the LRCLK, or can be achieved by

selecting the external BCLK or LRCLK signal as a reference input to the FLL, as a source for SYSCLK.

If the AIF clock domain is not synchronized with the LRCLK, clicks arising from dropped or repeated audio samples occur,

due to the inherent tolerances of multiple, asynchronous, system clocks. See Section 5.4 for further details on valid

clocking configurations.

4.16.7 BCLK and LRCLK Control

The digital audio interfaces (AIF1–AIF3) use BCLK and LRCLK signals for synchronization. In Master Mode, these are

output signals, generated by the CS47L35. In Slave Mode, these are input signals to the CS47L35. It is also possible to

support mixed master/slave operation.

The BCLK and LRCLK signals are controlled as shown in Fig. 4-64. See Section 4.7 for details of the associated control

fields.

Note that the BCLK and LRCLK signals are synchronized to SYSCLK. See Section 4.3.13 for further details.

R338 (0x0152)

Rate_Estimator_1

TRIG_ON_

STARTUP

Automatic Sample-Rate Detection Start-Up select

0 = Do not trigger Write Sequencer on initial detection

1 = Always trigger the Write Sequencer on sample-rate detection

3:1

LRCLK_SRC[2:0]

000

Automatic Sample-Rate Detection source

000 = AIF1LRCLK

010 = AIF2LRCLK

100 = AIF3LRCLK

All other codes are reserved

RATE_EST_ENA

Automatic Sample-Rate Detection control

0 = Disabled

1 = Enabled

R339 (0x0153)

Rate_Estimator_2

4:0

SAMPLE_RATE_

DETECT_A[4:0]

0x00

Automatic Detection Sample Rate A

(Up to four different sample rates can be configured for automatic detection.)

Field coding is same as SAMPLE_RATE_n.

R340 (0x0154)

Rate_Estimator_3

4:0

SAMPLE_RATE_

DETECT_B[4:0]

0x00

Automatic Detection Sample Rate B

(Up to four different sample rates can be configured for automatic detection.)

Field coding is same as SAMPLE_RATE_n.

R341 (0x0155)

Rate_Estimator_4

4:0

SAMPLE_RATE_

DETECT_C[4:0]

0x00

Automatic Detection Sample Rate C

(Up to four different sample rates can be configured for automatic detection.)

Field coding is same as SAMPLE_RATE_n.

R342 (0x0156)

Rate_Estimator_5

4:0

SAMPLE_RATE_

DETECT_D[4:0]

0x00

Automatic Detection Sample Rate D

(Up to four different sample rates can be configured for automatic detection.)

Field coding is same as SAMPLE_RATE_n.

Table 4-93. Clocking Control (Cont.)

Bit

Label

Default

Description

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