CS47L35 datasheet(93/300 Pages) CIRRUS

93 / 300 page

DS1085F3

CS47L35

4.5 DSP Peripheral Control

4.5.2

Event Loggers

The CS47L35 provides four event log functions, supporting multichannel, edge-sensitive monitoring and recording of

internal or external signals.

4.5.2.1 Overview

The event loggers allow status information to be captured from a large number of sources, to be prioritized and acted upon

as required. For the purposes of the event loggers, an event is recorded when a logic transition (edge) is detected on a

selected signal source.

The logged events are held in a FIFO buffer, which is managed by the application software. A 32-bit time stamp, derived

from one of the general-purpose timers, is associated and recorded with each FIFO index, to provide a comprehensive

record of the detected events.

Each event logger must be associated with one of the general-purpose timers. The selected timer is the source of time

stamp data for any logged events. If DSPCLK is disabled, the timer also provides the clock source for the event logger. (If

DSPCLK is enabled, DSPCLK is used as the clock source instead.)

A maximum of one event per cycle of the clock source can be logged. If more than one event occurs within the cycle time,

the highest priority (lowest channel number) event is logged at the rising edge of the clock. In this case, any lower priority

events is queued, and is logged as soon as no higher priority events are pending. It is possible for recurring events on a

high-priority channel to be logged, while low-priority ones remain queued. Note that recurring instances of events that are

queued would not be logged.

The event logger can use a slow clock (e.g., 32 kHz), but higher clock frequencies may also be commonly used, depending

on the application and use case. The clock frequency determines the maximum possible event logging rate.

4.5.2.2 Event Logger Control

The event logger is enabled by setting EVENTLOGn_ENA (where n identifies the respective event logger, 1–4).

R262660 (0x40204)

MIF1_TX_3

31:24 MIF1_TX_BYTE12[7:0]

0x00

TX Byte 12

23:16 MIF1_TX_BYTE11[7:0]

0x00

TX Byte 11

15:8 MIF1_TX_BYTE10[7:0]

0x00

TX Byte 10

7:0 MIF1_TX_BYTE9[7:0]

0x00

TX Byte 9

R262662 (0x40206)

MIF1_TX_4

31:24 MIF1_TX_BYTE16[7:0]

0x00

TX Byte 16

23:16 MIF1_TX_BYTE15[7:0]

0x00

TX Byte 15

15:8 MIF1_TX_BYTE14[7:0]

0x00

TX Byte 14

7:0 MIF1_TX_BYTE13[7:0]

0x00

TX Byte 13

R262912 (0x40300)

MIF1_RX_1

31:24 MIF1_RX_BYTE4[7:0]

0x00

RX Byte 4

23:16 MIF1_RX_BYTE3[7:0]

0x00

RX Byte 3

15:8 MIF1_RX_BYTE2[7:0]

0x00

RX Byte 2

7:0 MIF1_RX_BYTE1[7:0]

0x00

RX Byte 1

R262914 (0x40302)

MIF1_RX_2

31:24 MIF1_RX_BYTE8[7:0]

0x00

RX Byte 8

23:16 MIF1_RX_BYTE7[7:0]

0x00

RX Byte 7

15:8 MIF1_RX_BYTE6[7:0]

0x00

RX Byte 6

7:0 MIF1_RX_BYTE5[7:0]

0x00

RX Byte 5

R262916 (0x40304)

MIF1_RX_3

31:24 MIF1_RX_BYTE12[7:0]

0x00

RX Byte 12

23:16 MIF1_RX_BYTE11[7:0]

0x00

RX Byte 11

15:8 MIF1_RX_BYTE10[7:0]

0x00

RX Byte 10

7:0 MIF1_RX_BYTE9[7:0]

0x00

RX Byte 9

R262918 (0x40306)

MIF1_RX_4

31:24 MIF1_RX_BYTE16[7:0]

0x00

RX Byte 16

23:16 MIF1_RX_BYTE15[7:0]

0x00

RX Byte 15

15:8 MIF1_RX_BYTE14[7:0]

0x00

RX Byte 14

7:0 MIF1_RX_BYTE13[7:0]

0x00

RX Byte 13

Table 4-30. Master Interface (MIF1) Control (Cont.)

Bit

Label

Default

Description

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