CS47L35 datasheet(15/300 Pages) CIRRUS

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DS1085F3

CS47L35

3 Characteristics and Specifications

DAC to speaker output

(SPKOUTP+SPKOUTN,

Load = 4

, 15 H, BTL)

Maximum output power

SPKVDD = 5.0 V, 1% THD+N

SPKVDD = 4.2 V, 1% THD+N

SPKVDD = 3.6 V, 1% THD+N

—

2.7

1.9

1.4

—

SNR, defined in Table 3-1

A-weighted, output signal = 2.83 VRMS —

127

—

Dynamic range, defined in Table 3-1

A-weighted, –60 dBFS input —

102

—

THD, defined in Table 3-1

PO = 1.0 W —

–71

—

THD+N, defined in Table 3-1

PO = 1.0 W —

–70

—

THD, defined in Table 3-1

PO = 0.5 W —

–71

—

THD+N, defined in Table 3-1

PO = 0.5 W —

–70

—

Output noise floor

A-weighted —

1.3

—

VRMS

PSRR (DBVDDn, CPVDD1, AVDD),

defined in Table 3-1

100 mV (peak-peak) 217 Hz

100 mV (peak-peak) 10 kHz

—

125

—

PSRR (DCVDD, FLLVDD, CPVDD2),

defined in Table 3-1

100 mV (peak-peak) 217 Hz

100 mV (peak-peak) 10 kHz

—

125

105

—

PSRR (SPKVDD),

defined in Table 3-1

100 mV (peak-peak) 217 Hz

100 mV (peak-peak) 10 kHz

—

120

—

Table 3-10. Digital Input/Output

The following electrical characteristics are valid across the full range of recommended operating conditions.

Parameter

Minimum

Typical

Maximum

Units

Digital I/O (except

DMICDAT1/2 and

DMICCLK1/2) 1,3

1.Digital I/O is referenced to DBVDD1 or DBVDD2.

Input HIGH level

VDBVDDn = 1.71–1.98 V

VDBVDDn = 2.5 V ±10%

VDBVDDn = 3.3 V ±10%

0.75

DBVDDn

0.8

DBVDDn

0.7

DBVDDn

—

Input LOW level

VDBVDDn = 1.71–1.98 V

VDBVDDn = 2.5 V ±10%

VDBVDDn = 3.3 V ±10%

—

0.3

DBVDDn

0.25

DBVDDn

0.2

DBVDDn

Output HIGH level

(IOH = 1 mA)

VDBVDDn = 1.71–1.98 V

VDBVDDn = 2.5 V ±10%

VDBVDDn = 3.3 V ±10%

0.75

DBVDDn

0.65

DBVDDn

0.7

DBVDDn

—

Output LOW level

(IOL = 1mA)

VDBVDDn = 1.71–1.98 V

VDBVDDn = 2.5 V ±10%

VDBVDDn = 3.3 V ±10%

—

0.25

DBVDDn

0.3

DBVDDn

0.15

DBVDDn

Input capacitance

—

Input leakage

–1

—

A

Pull-up/pull-down resistance (where applicable)

—



DMIC I/O

(DMICDAT1/2 and

DMICCLK1/2) 2,3

2.DMICDAT1/2 and DMICCLK1/2 are referenced to a selectable supply, VSUP, according to the INn_DMIC_SUP fields.

3.Note that digital input pins should not be left unconnected or floating.

DMICDATn input HIGH Level

0.65

 VSUP

——

DMICDATn input LOW Level

—

0.35

 VSUP

DMICCLKn output HIGH Level

IOH = 1 mA

0.8

 VSUP

——

DMICCLKn output LOW Level

IOL = –1 mA

—

0.2

 VSUP

Input capacitance

—

Input leakage

–1

—

A

GPIOn

Clock output frequency

GPIO pin as OPCLK or FLL output

—

MHz

Table 3-9. Input/Output Path Characteristics (Cont.)

Test conditions (unless specified otherwise): DBVDD1 = DBVDD2 = CPVDD1 = AVDD = 1.8 V, DCVDD = FLLVDD = CPVDD2 = 1.2 V; MICVDD = 2.5 V

(powered from internal LDO); SPKVDD = 4.2 V; TA = +25ºC; 1 kHz sinusoid signal; Fs = 48 kHz; PGA gain = 0 dB, 24-bit audio data.

Parameter

Min Typ Max Units

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