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CS47L35 датащи(PDF) 192 Page - Cirrus Logic |
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CS47L35 датащи(HTML) 192 Page - Cirrus Logic |
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192 / 300 page ![]() 192 DS1085F3 CS47L35 4.16 Clocking and Sample Rates R257 (0x0101) System_Clock_1 15 SYSCLK_FRAC 0 SYSCLK Frequency 0 = SYSCLK is a multiple of 6.144MHz 1 = SYSCLK is a multiple of 5.6448MHz 10:8 SYSCLK_ FREQ[2:0] 100 SYSCLK Frequency 000 = 6.144 MHz (5.6448 MHz) 001 = 12.288 MHz (11.2896 MHz) 010 = 24.576 MHz (22.5792 MHz) 011 = 49.152 MHz (45.1584 MHz) 100 = 98.304 MHz (90.3168 MHz) All other codes are reserved The frequencies in brackets apply for 44.1 kHz–related sample rates only (i.e., SAMPLE_RATE_n = 01XXX). 6 SYSCLK_ENA 0 SYSCLK Control 0 = Disabled 1 = Enabled SYSCLK should only be enabled after the applicable clock source has been configured and enabled. Set this bit to 0 when reconfiguring the clock sources. All digital core (audio mixer) x_SRC fields must be cleared before clearing SYSCLK_ENA = 0. 3:0 SYSCLK_ SRC[3:0] 0100 SYSCLK Source 0000 = MCLK1 0001 = MCLK2 0100 = FLL1 1000 = AIF1BCLK 1001 = AIF2BCLK 1010 = AIF3BCLK All other codes are reserved R258 (0x0102) Sample_rate_1 4:0 SAMPLE_RATE_ 1[4:0] 0x11 Sample Rate 1 Select 0x00 = None 0x01 = 12 kHz 0x02 = 24 kHz 0x03 = 48 kHz 0x04 = 96 kHz 0x05 = 192 kHz 0x09 = 11.025 kHz 0x0A = 22.05 kHz 0x0B = 44.1 kHz 0x0C = 88.2 kHz 0x0D = 176.4 kHz 0x11 = 8 kHz 0x12 = 16 kHz 0x13 = 32 kHz All other codes are reserved R259 (0x0103) Sample_rate_2 4:0 SAMPLE_RATE_ 2[4:0] 0x11 Sample Rate 2 Select Field coding is same as SAMPLE_RATE_1. R260 (0x0104) Sample_rate_3 4:0 SAMPLE_RATE_ 3[4:0] 0x11 Sample Rate 3 Select Field coding is same as SAMPLE_RATE_1. R266 (0x010A) Sample_rate_1_ status 4:0 SAMPLE_RATE_ 1_STS[4:0] 0x00 Sample Rate 1 Status (Read only) Field coding is same as SAMPLE_RATE_1. R267 (0x010B) Sample_rate_2_ status 4:0 SAMPLE_RATE_ 2_STS[4:0] 0x00 Sample Rate 2 Status (Read only) Field coding is same as SAMPLE_RATE_1. R268 (0x010C) Sample_rate_3_ status 4:0 SAMPLE_RATE_ 3_STS[4:0] 0x00 Sample Rate 3 Status (Read only) Field coding is same as SAMPLE_RATE_1. Table 4-93. Clocking Control (Cont.) Register Address Bit Label Default Description |
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