CS47L35 datasheet(186/300 Pages) CIRRUS

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DS1085F3

CS47L35

4.16 Clocking and Sample Rates

The CS47L35 requires a clock reference for its internal functions and also for the input (ADC) paths, output (DAC) paths,

and digital audio interfaces. Under typical clocking configurations, all commonly used audio sample rates can be derived

directly from the external reference; for additional flexibility, the CS47L35 incorporates an FLL circuit to perform frequency

conversion and filtering.

External clock signals may be connected via MCLK1 and MCLK2. These inputs are referenced to the DBVDD1 and

DBVDD2 power domains respectively. In AIF Slave Modes, the BCLK signals may be used as a reference for the system

clocks. The SLIMbus interface can provide the clock reference, when used as the input to the FLL. To avoid audible

glitches, all clock configurations must be set up before enabling playback.

4.16.1 System Clocking Overview

The CS47L35 supports two primary clock domains—SYSCLK and DSPCLK.

The SYSCLK clock domain is the reference clock for all the audio signal paths on the CS47L35. Up to three different

sample rates may be independently selected for specific audio interfaces and other input/output signal paths.

The DSPCLK clock domain is the reference clock for the programmable DSP cores on the CS47L35. A wide range of

DSPCLK frequencies can be supported, and a programmable clock divider is provided for each DSP core, allowing the

DSP clocking (and power consumption) to be optimized according to the applicable processing requirements of each DSP

core. See Section 4.4 for further details.

Note that there is no requirement for DSPCLK to be synchronized to SYSCLK. The DSPCLK controls the software

execution in the DSP cores; audio outputs from the DSP cores are synchronized to SYSCLK, regardless of the applicable

DSPCLK rate.

Excluding the DSP cores, each subsystem within the CS47L35 digital core is clocked at a dynamically controlled rate,

limited by the SYSCLK frequency. For maximum signal mixing and processing capacity, it is recommended that the

highest possible SYSCLK frequency is configured.

The DSP cores are clocked at the DSPCLK rate (or supported divisions of the DSPCLK frequency). The DSPCLK

configuration must ensure that sufficient clock cycles are available for the processing requirements of each DSP core. The

requirements vary, according to the particular software that is in use.

Table 4-91. Interrupt Control Registers

Bit

Label

Default

Description

R6784 (0x1A80)

IRQ1_CTRL

IM_IRQ1

IRQ1 Output Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

IRQ_POL

IRQ Output Polarity Select

0 = Noninverted (Active High)

1 = Inverted (Active Low)

IRQ_OP_CFG

IRQ Output Configuration

0 = CMOS

1 = Open drain

R6786 (0x1A82)

IRQ2_CTRL

IM_IRQ2

IRQ2 Output Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

R6816 (0x1AA0)

Interrupt_Raw_

Status_1

IRQ2_STS

IRQ2 Status. IRQ2_STS is the logical OR of all unmasked x_EINT2 interrupts.

0 = Not asserted

1 = Asserted

IRQ1_STS

IRQ1 Status. IRQ1_STS is the logical OR of all unmasked x_EINT1 interrupts.

0 = Not asserted

1 = Asserted

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