CS47L35 datasheet(81/300 Pages) CIRRUS

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DS1085F3

CS47L35

4.4 DSP Firmware Control

4.4.2

DSP Firmware Control

The configuration and control of the DSP firmware is described in the following subsections.

4.4.2.1 DSP Memory

The DSP memory (program, X-data, Y-data, and coefficient) is enabled by setting DSPn_MEM_ENA for the respective

DSP. This memory must be enabled (DSPn_MEM_ENA = 1) for read/write access, code execution, and DMA functions.

The DSP memory is disabled, and the contents lost, whenever the respective DSPn_MEM_ENA bit is cleared.

The DSPn_MEM_ENA bits are not affected by software reset; these bits remain in their previous state under software

reset conditions. Accordingly, the DSP memory contents are maintained through software reset, provided DCVDD is held

above its reset threshold.

The DSP firmware memory is always cleared under power-on reset, hardware reset, and Sleep Mode conditions. See

Section 5 for a summary of the CS47L35 reset behavior.

4.4.2.2 DSP Clocking

Clocking is required for each of the DSP processing blocks, when executing software or when supporting DMA functions.

(Note that clocking is not required for access to the firmware registers by the host processor.)

Clocking within each DSP is enabled and disabled automatically, as required by the respective DSP core and DMA

channel status.

The clock source for each DSP is derived from DSPCLK. See Section 4.16 for details of how to configure DSPCLK.

The clock frequency for each DSP is selected using the DSPn_CLK_SEL field (where n identifies the applicable DSP

block, 1 to 3). The DSP clock frequency must be less than or equal to the DSPCLK frequency.

Table 4-24. X-Data Memory and Clocking Control

Bit

Label

Default

Description

DSP1 Base Address = R1048064 (0x0F_FE00)

DSP2 Base Address = R1572352 (0x17_FE00)

DSP3 Base Address = R2096640 (0x1F_FE00)

Base address + 0x54

DSPn_Ext_window_A

DSPn_EXT_A_PSIZE16

0 = 32-bit

1 = 16-bit

Note that, in 32-Bit Mode, only the lower 24 bits can be accessed.

15:0 DSPn_EXT_A_PAGE[15:0]

0x0000 Sets the Base Address of Register Window A in X-memory.

Coded as LSB = 512 (0x200)

Base address + 0x56

DSPn_Ext_window_B

DSPn_EXT_B_PSIZE16

0 = 32-bit

1 = 16-bit

Note that, in 32-Bit Mode, only the lower 24 bits can be accessed.

15:0 DSPn_EXT_B_PAGE[15:0]

0x0000 Sets the Base Address of Register Window B in X-memory.

Coded as LSB = 512 (0x200)

Base address + 0x58

DSPn_Ext_window_C

DSPn_EXT_C_PSIZE16

0 = 32-bit

1 = 16-bit

Note that, in 32-Bit Mode, only the lower 24 bits can be accessed.

15:0 DSPn_EXT_C_PAGE[15:0]

0x0000 Sets the Base Address of Register Window C in X-memory.

Coded as LSB = 512 (0x200)

Base address + 0x5A

DSPn_Ext_window_D

DSPn_EXT_D_PSIZE16

0 = 32-bit

1 = 16-bit

Note that, in 32-Bit Mode, only the lower 24 bits can be accessed.

15:0 DSPn_EXT_D_PAGE[15:0]

0x0000 Sets the Base Address of Register Window D in X-memory.

Coded as LSB = 512 (0x200)

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