CS47L35 datasheet(189/300 Pages) CIRRUS

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DS1085F3

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CS47L35

4.16 Clocking and Sample Rates

• Input signal path enabled (INnx_ENA = 1)

• OPCLK enabled for GPIO output (OPCLK_ENA = 1)

• Output signal path enabled (OUT5x_ENA = 1, SPKOUTL_ENA = 1, HP1x_ENA = 1)

• Digital audio interface path enabled (AIFnTXm_ENA = 1, AIFnRXm_ENA = 1)

• Digital audio interface clocks enabled (AIFn_BCLK_FRC = 1, AIFn_LRCLK_FRC = 1)

• SPDIF output enabled (SPD1_ENA = 1)

• Digital Core Mixer enabled (x_SRCn > 0x00)

• Haptic generator enabled (HAP_CTRL > 00)

• Tone generator enabled (TONEn_ENA = 1)

• PWM generator enabled (PWMn_ENA = 1)

• EQ, DRC, or LHPF processor enabled (EQn_ENA = 1, DRCnx_ENA = 1, LHPFn_ENA = 1)

• ISRC channel enabled (ISRCn_INTm_ENA = 1, ISRCn_DECm_ENA = 1)

• SLIMbus data channel enabled (SLIMTXn_ENA = 1, SLIMRXn_ENA = 1)

• Noise generator enabled (NOISE_GEN_ENA = 1)

• Timer enabled, with SYSCLK as clock source (TIMERn_RUNNING_STS = 1 and TIMERn_REFCLK_SRC = 0x8)

• DSP Core firmware requires access to registers below 0x40000

If reconfiguration of the SYSCLK source or frequency is required, and it is not possible to disable all of the

SYSCLK-dependent subsystems, then the control-write sequencer must be used for the reconfiguration of SYSCLK. The

control sequence should apply the following actions:

• Clear SYSCLK_ENA to 0

• Write updates to SYSCLK_SRC, SYSCLK_FREQ, and SYSCLK_FRAC

• Set SYSCLK_ENA to 1

The CS47L35 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the

commanded signal paths and processing functions. If the frequency is too low, an attempt to enable a signal path or

processing function fails. Note that active signal paths are not affected under such circumstances.

4.16.5 DSPCLK Control

The DSPCLK clock may be provided directly from external inputs (MCLK, or Slave Mode BCLK inputs). Alternatively,

DSPCLK can be derived using the integrated FLL, with MCLK, BCLK, LRCLK, or SLIMCLK as a reference. The DSPCLK

must be configured and enabled, if running firmware applications on any of the DSP cores.

The required DSPCLK frequency depends on the requirements of firmware loaded on the DSP cores. The DSP cores are

clocked at the DSPCLK rate or at supported divisions of the DSPCLK frequency. The DSPCLK configuration must ensure

that sufficient clock cycles are available for the processing requirements of each DSP core. The requirements vary,

according to the particular software that is in use.

A configurable clock divider is provided for each DSP core, allowing the DSP clocking (and power consumption) to be

optimized according to the applicable processing requirements of each DSP core; see Section 4.4 for details.

DSP_CLK_FREQ_RANGE must be configured for the applicable DSPCLK frequency. Note that, if the DSPCLK frequency

is equal to one of the threshold frequencies quoted, the higher range setting should be selected. For example, if the

DSPCLK frequency is 37.5 MHz, DSP_CLK_FREQ_RANGE should be set to 011.

DSP_CLK_SRC is used to select the DSPCLK source, as described in Table 4-93. The source may be MCLKn,

AIFnBCLK, or FLL. If the FLL circuit is selected as the source, the FLL must be enabled and configured, as described in

Section 4.16.9.

Note: If the FLL is selected as DSPCLK source, two different clock frequencies are available. For most use cases, the

FLL output frequency is divided by two, when used as the DSPCLK source; this enables DSPCLK frequencies in

the range 135–150 MHz. A divide-by-six option is also available, supporting low-power DSP operation with

DSPCLK frequencies in the range 45–50 MHz.

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