CS47L35 datasheet(48/300 Pages) CIRRUS

48 / 300 page

DS1085F3

CS47L35

4.3 Digital Core

The hexadecimal numbers in Fig. 4-16 indicate the corresponding x_SRCn setting for selection of that signal as an input

to another digital-core function.

The EQ blocks should be kept disabled (EQn_ENA = 0) if SYSCLK is not enabled. The x_SRCn fields for all digital core

functions should be held at 0x00 if SYSCLK is not enabled. SYSCLK must be present and enabled before selecting other

values for these fields. See Section 4.16.4 for further details (including requirements for reconfiguring SYSCLK while

digital core functions are enabled).

The sample rate for the EQ function is configured using FX_RATE; see Table 4-21. Note that the EQ, DRC, and LHPF

functions must be configured for the same sample rate. Sample-rate conversion is required when routing the EQ signal

paths to any signal chain that is configured for a different sample rate.

The FX_RATE field must not be changed if any of the associated x_SRCn fields is nonzero. The associated x_SRCn fields

must be cleared before writing a new value to FX_RATE. A minimum delay of 125

s must be allowed between clearing

the x_SRCn fields and writing to FX_RATE. See Table 4-21 for details.

The cut-off or center frequencies for the five-band EQ are set by using the coefficients held in the registers identified in

Table 4-8. These coefficients are derived using tools provided in Cirrus Logic’s WISCE™ evaluation-board control

software; please contact your Cirrus Logic representative for details.

The control registers associated with the EQ functions are described in Table 4-9.

Table 4-8. EQ Coefficient Registers

EQ1

R3602 (0x0E10) to R3620 (0x0E24)

EQ2

R3624 (0x0E28) to R3642 (0x0E3A)

EQ3

R3646 (0x0E3E) to R3664 (0x0E53)

EQ4

R3668 (0x0E54) to R3686 (0x0E66)

Table 4-9. EQ Enable and Gain Control

Bit

Label

Default

Description

R3585 (0x0E01)

FX_Ctrl2

15:4 FX_STS[11:0]

0x00 LHPF, DRC, EQ Enable Status. Indicates the status of each of the respective

signal-processing functions. Each bit is coded as follows:

0 = Disabled

1 = Enabled

[11] = EQ4

[10] = EQ3

[9] = EQ2

[8] = EQ1

[7] = DRC2 (Right)

[6] = DRC2 (Left)

[5] = DRC1 (Right)

[4] = DRC1 (Left)

[3] = LHPF4

[2] = LHPF3

[1] = LHPF2

[0] = LHPF1

R3600 (0x0E10)

EQ1_1

15:11 EQ1_B1_GAIN[4:0]

0x0C EQ1 Band 1 Gain 1 (–12 dB to +12 dB in 1-dB steps)

10:6 EQ1_B2_GAIN[4:0]

0x0C EQ1 Band 2 Gain 1 (–12 dB to +12 dB in 1-dB steps)

5:1

EQ1_B3_GAIN[4:0]

0x0C EQ1 Band 3 Gain 1 (–12 dB to +12 dB in 1-dB steps)

EQ1_ENA

EQ1 Enable

0 = Disabled

1 = Enabled

R3601 (0x0E11)

EQ1_2

15:11 EQ1_B4_GAIN[4:0]

0x0C EQ1 Band 4 Gain 1 (–12 dB to +12 dB in 1-dB steps)

10:6 EQ1_B5_GAIN[4:0]

0x0C EQ1 Band 5 Gain 1 (–12 dB to +12 dB in 1-dB steps)

EQ1_B1_MODE

EQ1 Band 1 Mode

0 = Shelving filter

1 = Peak filter

R3602 (0x0E12) to

R3620 (0x0E24)

15:0 EQ1_B1_*

EQ1_B2_*

EQ1_B3_*

EQ1_B4_*

EQ1_B5_*

—

EQ1 Frequency Coefficients. Refer to WISCE evaluation board control software for

the derivation of these field values.

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