| поискавой системы для электроныых деталей |
|
CS47L35 датащи(PDF) 55 Page - Cirrus Logic |
|
|
|||||||||||||||||||||||||||||
CS47L35 датащи(HTML) 55 Page - Cirrus Logic |
|
55 / 300 page ![]() DS1085F3 55 CS47L35 4.3 Digital Core The DRC signal-detect function is enabled by setting DRCn_SIG_DET. Note that the respective DRCn must also be enabled. The detection threshold is either a peak level (crest factor) or an RMS level, depending on DRCn_SIG_DET_ MODE. When peak level is selected, the threshold is determined by DRCn_SIG_DET_PK, which defines the applicable crest factor (peak-to-RMS ratio) threshold. If RMS level is selected, the threshold is set using DRCn_SIG_DET_RMS. The DRC signal-detect function is an input to the interrupt control circuit and can be used to trigger an interrupt event; see Section 4.15. The control-write sequencer can be triggered by the DRC1 signal-detect function. This is enabled by setting DRC1_ WSEQ_SIG_DET_ENA. See Section 4.18. Note that signal detection is supported on DRC1 and DRC2, but the triggering of the control-write sequencer is available on DRC1 only. 4.3.5.7 DRC Register Controls The DRC1 control registers are described in Table 4-13. Table 4-13. DRC1 Control Registers Register Address Bit Label Default Description R3585 (0x0E01) FX_Ctrl2 15:4 FX_STS[11:0] 0x00 LHPF, DRC, EQ enable status. Indicates the status of each of the respective signal-processing functions. Each bit is coded as follows: 0 = Disabled 1 = Enabled [11] = EQ4 [10] = EQ3 [9] = EQ2 [8] = EQ1 [7] = DRC2 (Right) [6] = DRC2 (Left) [5] = DRC1 (Right) [4] = DRC1 (Left) [3] = LHPF4 [2] = LHPF3 [1] = LHPF2 [0] = LHPF1 R3712 (0x0E80) DRC1_ctrl1 15:11 DRC1_SIG_ DET_RMS[4:0] 0x00 DRC1 Signal-Detect RMS Threshold. RMS signal level for signal-detect to be indicated when DRC1_SIG_DET_MODE = 1. 0x00 = –30 dB 0x01 = –31.5 dB …. (1.5-dB steps) 0x1E = –75 dB 0x1F = –76.5 dB 10:9 DRC1_SIG_ DET_PK[1:0] 00 DRC1 Signal-Detect Peak Threshold. This is the Peak/RMS ratio, or Crest Factor, level for signal-detect to be indicated when DRC1_SIG_DET_MODE = 0. 00 = 12 dB 01 = 18 dB 10 = 24 dB 11 = 30 dB 8 DRC1_NG_ENA 0 DRC1 Noise-Gate Enable 0 = Disabled 1 = Enabled 7 DRC1_SIG_ DET_MODE 0 DRC1 Signal-Detect Mode 0 = Peak threshold mode 1 = RMS threshold mode 6 DRC1_SIG_DET 0 DRC1 Signal-Detect Enable 0 = Disabled 1 = Enabled 5 DRC1_KNEE2_ OP_ENA 0 DRC1 KNEE2_OP Enable 0 = Disabled 1 = Enabled 4 DRC1_QR 1 DRC1 Quick-release Enable 0 = Disabled 1 = Enabled 3 DRC1_ANTICLIP 1 DRC1 Anticlip Enable 0 = Disabled 1 = Enabled 2 DRC1_WSEQ_ SIG_DET_ENA 0 DRC1 Signal-Detect Write Sequencer Select 0 = Disabled 1 = Enabled |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |