CS47L35 datasheet(50/300 Pages) CIRRUS

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DS1085F3

CS47L35

4.3 Digital Core

The CS47L35 automatically checks to confirm whether the SYSCLK frequency is high enough to support the commanded

EQ and digital mixing functions. If an attempt is made to enable an EQ signal path, and there are insufficient SYSCLK

cycles to support it, the attempt does not succeed. Note that any signal paths that are already active are not affected under

such circumstances.

The FX_STS field in register R3585 indicates the status of each of the EQ, DRC, and LHPF signal paths. If an

underclocked error condition occurs, this field indicates which EQ, DRC, or LHPF signal paths have been enabled.

The status bits in registers R1600–R2936 indicate the status of each of the digital mixers. If an underclocked error

condition occurs, these bits indicate which mixers have been enabled.

4.3.5

Dynamic Range Control (DRC)

The digital core provides two stereo DRC processing blocks, as shown in Fig. 4-17. A four-input mixer is associated with

each DRC input channel. The input sources are selectable in each case, and independent volume control is provided for

each path. The stereo DRC blocks support two outputs each.

The function of the DRC is to adjust the signal gain in conditions where the input amplitude is unknown or varies over a

wide range, for example, when recording from microphones built into a handheld system or to restrict the dynamic range

of an output signal path.

To improve intelligibility in the presence of loud impulsive noises, the DRC can apply compression and automatic level

control to the signal path. It incorporates anticlip and quick-release features for handling transients.

The DRC also incorporates a noise-gate function that provides additional attenuation of very low-level input signals. This

means that the signal path is quiet when no signal is present, giving an improvement in background noise level under these

conditions.

A signal-detect function is provided within the DRC; this can be used to detect the presence of an audio signal and to

trigger other events. It can also be used as an interrupt event or to trigger the control-write sequencer. Note that DRC

triggering of the control-write sequencer is supported for DRC1 only.

Table 4-10. EQ Gain-Control Range

EQ Gain Setting Gain (dB) EQ Gain Setting Gain (dB)

00000

–12

01101

00001

–11

01110

00010

–10

01111

00011

–9

10000

00100

–8

10001

00101

–7

10010

00110

–6

10011

00111

–5

10100

01000

–4

10101

01001

–3

10110

+10

01010

–2

10111

+11

01011

–1

11000

+12

01100

11001–11111

Reserved

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