CS47L35 datasheet(62/300 Pages) CIRRUS

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DS1085F3

CS47L35

4.3 Digital Core

The x_SRCn fields for all digital core functions should be held at 0x00 if SYSCLK is not enabled—SYSCLK must be

present and enabled before selecting other values for these fields. See Section 4.16.4 for further details (including

requirements for reconfiguring SYSCLK while digital core mixers are enabled).

The sample rate for each of the DSP functions is configured using the respective DSPn_RATE field; see Table 4-21.

Sample-rate conversion is required when routing the DSPn signal paths to any signal chain that is configured for a different

sample rate.

The DSPn_RATE fields must not be changed if any of the respective x_SRCn fields is nonzero. The associated x_SRCn

fields must be cleared before writing new values to DSPn_RATE. A minimum delay of 125

s must be allowed between

clearing the x_SRCn fields and writing to the associated DSPn_RATE fields. See Table 4-21 for details.

The CS47L35 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the required

DSP mixing functions. If the frequency is too low, an attempt to enable a DSP mixer path fails. Note that active signal paths

are not affected under such circumstances.

The status bits in registers R1600–R2936 indicate the status of each of the digital mixers. If an underclocked error

condition occurs, these bits indicate which mixers have been enabled.

4.3.8

S/PDIF Output Generator

The CS47L35 incorporates an IEC-60958-3–compatible S/PDIF output generator, as shown in Fig. 4-21; this provides a

stereo S/PDIF output on a GPIO pin. The S/PDIF transmitter allows full control over the S/PDIF validity bits and channel

status information.

The input sources to the S/PDIF transmitter are selectable for each channel, and independent volume control is provided

for each path. The *TX1 and *TX2 fields control Channels A and B (respectively) of the S/PDIF output.

The S/PDIF signal can be output directly on a GPIO pin. See Section 4.14 to configure a GPIO pin for this function.

Note that the S/PDIF signal cannot be selected as input to the digital mixers or signal-processing functions within the

CS47L35 digital core.

Figure 4-21. Digital-Core S/PDIF Output Generator

The S/PDIF input control fields (see Fig. 4-21) are located at register addresses R2048–R2057 (0x0800–0x0809).

The full list of digital mixer control registers (R1600–R2936) is provided in Section 6. Generic register field definitions are

provided in Table 4-7.

The x_SRCn fields select the input sources for the two S/PDIF channels. Note that the selected input sources must be

synchronized to the SYSCLK clocking domain, and configured for the same sample rate as the S/PDIF generator.

Sample-rate conversion functions are available to support flexible interconnectivity; see Section 4.3.14.

SPDIF1TX1_VOL

SPDIF1TX2_VOL

SPDIF1TX2_SRC

SPDIF1TX1_SRC

GPIO

(GPn_FN = 0x04C)

S/PDIF

SPD1_ENA

SPD1_RATE

Channel A

Channel B

…

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