CS47L35 datasheet(45/300 Pages) CIRRUS

45 / 300 page

DS1085F3

CS47L35

4.3 Digital Core

The OUT_RATE, AIFn_RATE, or SLIMTXn_RATE fields must not be changed if any of the respective x_SRCn fields is

nonzero. The associated x_SRCn fields must be cleared before writing new values to OUT_RATE, AIFn_RATE, or

SLIMTXn_RATE. A minimum delay of 125

s must be allowed between clearing the x_SRCn fields and writing to the

associated OUT_RATE, AIFn_RATE, or SLIMTXn_RATE fields. See Table 4-21 for details.

The CS47L35 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the output

mixer paths. If the frequency is too low, an attempt to enable an output mixer path fails. Note that active signal paths are

not affected under such circumstances.

The status bits in registers R1600–R2936 indicate the status of each of the digital mixers. If an underclocked error

condition occurs, these bits indicate which mixers have been enabled.

Figure 4-13. Digital-Core AIF Outputs

AIF3TXnMIX_SRC1

AIF3TXnMIX_SRC3

AIF3TXnMIX_SRC4

AIF3TXnMIX_SRC2

AIF3 TXn

AIF2TXnMIX_SRC1

AIF2TXnMIX_SRC3

AIF2TXnMIX_SRC4

AIF2TXnMIX_SRC2

AIF2 TXn

AIF1TXnMIX_SRC1

AIF1TXnMIX_SRC3

AIF1TXnMIX_SRC4

AIF1TXnMIX_SRC2

AIF1 TXn

AIF3TXnMIX_VOL2

AIF3TXnMIX_VOL3

AIF3TXnMIX_VOL4

AIF3TXnMIX_VOL1

AIF2TXnMIX_VOL2

AIF2TXnMIX_VOL3

AIF2TXnMIX_VOL4

AIF2TXnMIX_VOL1

AIF1TXnMIX_VOL2

AIF1TXnMIX_VOL3

AIF1TXnMIX_VOL4

AIF1TXnMIX_VOL1

…

CS47L35 supports six AIF1 output mixers, i.e., n = 1–6

CS47L35 supports two AIF2 output mixers, i.e., n = 1 or 2

CS47L35 supports two AIF3 output mixers, i.e., n = 1 or 2

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