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CS47L35 датащи(PDF) 42 Page - Cirrus Logic |
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CS47L35 датащи(HTML) 42 Page - Cirrus Logic |
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42 / 300 page ![]() 42 DS1085F3 CS47L35 4.3 Digital Core 4.3.1 Digital-Core Mixers The CS47L35 provides an extensive digital mixing capability. The digital-core mixing and signal-processing blocks are shown in Fig. 4-11. A four-input digital mixer is associated with many of these functions, as shown. The digital mixer circuit is identical in each instance, providing up to four selectable input sources, with independent volume control on each input. The control registers associated with the digital-core signal paths are shown in Fig. 4-12–Fig. 4-27. The full list of digital mixer control registers (R1600–R2936) is provided in Section 6. Further description of the associated control registers is provided throughout Section 4.3. Generic register field definitions are provided in Table 4-7. The digital mixer input sources are selected using the associated x_SRCn fields; the volume control is implemented via the associated x_VOLn fields. The ISRC and DSP auxiliary input functions support selectable input sources, but do not incorporate any digital mixing. The respective input source (x_SRCn) fields are identical to those of the digital mixers. The x_SRCn fields select the input sources for the respective mixer or signal-processing block. Note that the selected input sources must be configured for the same sample rate as the blocks to which they are connected. Sample-rate conversion functions are available to support flexible interconnectivity; see Section 4.3.14. The x_SRCn fields for all digital core functions should be held at 0x00 if SYSCLK is not enabled—SYSCLK must be present and enabled before selecting other values for these fields. See Section 4.16.4 for further details (including requirements for reconfiguring SYSCLK while digital core mixers are enabled). A status bit is associated with each configurable input source. If an underclocked error condition occurs, these bits indicate which signal paths have been enabled. The generic register field definition for the digital mixers is provided in Table 4-7. |
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