CS47L35 datasheet(77/300 Pages) CIRRUS

77 / 300 page

DS1085F3

CS47L35

4.4 DSP Firmware Control

The CS47L35 digital core incorporates three DSP processing blocks, capable of running a wide range of

audio-enhancement functions. Different firmware configurations can be loaded onto each DSP, enabling the CS47L35 to

be highly customized for specific application requirements. Full read/write access to the device register map is supported

from each DSP core, including access to the firmware registers of the other DSPs. Synchronization of different DSPs is

supported, and shared data memory space is provided for the DSP2 and DSP3 blocks; these features enable enhanced

processing capabilities for the associated DSPs.

Examples of the DSP functions include multiband compressor (MBC), and the SoundClear™ suite of audio processing

algorithms. Note that it is possible to implement more than one type of audio enhancement function on a single DSP; the

precise combinations of functions vary from one firmware configuration to another.

The DSP blocks each employ the same internal architecture and provide an equivalent processing capability. Note that

the DSPs differ in terms of the firmware memory sizes associated with each. The DSPs can be clocked at up to 150MHz,

corresponding to 150 MIPS each.

R3828 (0x0EF4)

ISRC2_CTRL_2

14:11 ISRC2_FSL[3:0]

0000

ISRC2 Low Sample Rate (Sets the lower of the ISRC2 sample rates)

0000 = SAMPLE_RATE_1

0001 = SAMPLE_RATE_2

0010 = SAMPLE_RATE_3

All other codes are reserved.

The selected sample rate is valid in the range 8 kHz to 192 kHz.

All ISRC2_INTn_SRC fields must be cleared before changing ISRC2_FSL.

R3829 (0x0EF5)

ISRC2_CTRL_3

ISRC2_INT1_ENA

ISRC2 INT1 Enable (Interpolation Channel 1 path from ISRC2_FSL rate to

ISRC2_FSH rate)

0 = Disabled

1 = Enabled

ISRC2_INT2_ENA

ISRC2 INT2 Enable (Interpolation Channel 2 path from ISRC2_FSL rate to

ISRC2_FSH rate)

0 = Disabled

1 = Enabled

ISRC2_INT3_ENA

ISRC2 INT3 Enable (Interpolation Channel 3 path from ISRC2_FSL rate to

ISRC2_FSH rate)

0 = Disabled

1 = Enabled

ISRC2_INT4_ENA

ISRC2 INT4 Enable (Interpolation Channel 4 path from ISRC2_FSL rate to

ISRC2_FSH rate)

0 = Disabled

1 = Enabled

ISRC2_DEC1_

ENA

ISRC2 DEC1 Enable (Decimation Channel 1 path from ISRC2_FSH rate to

ISRC2_FSL rate)

0 = Disabled

1 = Enabled

ISRC2_DEC2_

ENA

ISRC2 DEC2 Enable (Decimation Channel 2 path from ISRC2_FSH rate to

ISRC2_FSL rate)

0 = Disabled

1 = Enabled

ISRC2_DEC3_

ENA

ISRC2 DEC3 Enable (Decimation Channel 3 path from ISRC2_FSH rate to

ISRC2_FSL rate)

0 = Disabled

1 = Enabled

ISRC2_DEC4_

ENA

ISRC2 DEC4 Enable (Decimation Channel 4 path from ISRC2_FSH rate to

ISRC2_FSL rate)

0 = Disabled

1 = Enabled

Table 4-22. Digital-Core ISRC Control (Cont.)

Bit

Label

Default

Description

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