CS47L35 datasheet(86/300 Pages) CIRRUS

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DS1085F3

CS47L35

4.4 DSP Firmware Control

4.4.4

DSP Interrupts

The DSP cores provide inputs to the interrupt circuit and can be used to trigger an interrupt event when the associated

conditions occur. For each DSP, the following interrupts are provided:

• DMA interrupt—Asserted when all enabled DSP input (WDMA) channel buffers have been filled, and all enabled

DSP output (RDMA) channel buffers have been emptied

• DSP Start 1, DSP Start 2 interrupts—Asserted when the respective start signal is triggered

• DSP Busy interrupt—Asserted when the DSP is busy (i.e., when firmware execution or DMA processes are started)

The CS47L35 also provides 16 control bits that allow the DSP cores to generate programmable interrupt events. When a

1 is written to these bits (see Table 4-27), the respective DSP interrupt (DSP_IRQn_EINTx) is triggered. The associated

interrupt bits are latched once set; they can be polled at any time or used to control the IRQ signal.

See Section 4.15 for further details.

Base address +0x24

DSPn_RDMA_Buffer_3

31:16 DSPn_START_ADDRESS_

RDMA_BUFFER_5[15:0]

0x0000

DSPn RDMA Channel 5 Start Address

Field description is as above.

15:0 DSPn_START_ADDRESS_

RDMA_BUFFER_4[15:0]

0x0000

DSPn RDMA Channel 4 Start Address

Field description is as above.

Base address +0x30

DSPn_DMA_Config_1

23:16 DSPn_WDMA_CHANNEL_

ENABLE[7:0]

0x00

DSPn WDMA Channel Enable

There are eight WDMA channels; each bit of this field enables

the respective WDMA channel.

Each bit is coded as follows:

0 = Disabled

1 = Enabled

13:0 DSPn_DMA_BUFFER_

LENGTH[13:0]

0x0000

DSPn DMA Buffer Length

Selects the amount of data transferred in each DMA channel.

The LSB represents one 24-bit DSP memory word.

Base address +0x32

DSPn_DMA_Config_2

7:0

DSPn_WDMA_CHANNEL_

OFFSET[7:0]

0x00

DSPn WDMA Channel Offset

There are eight WDMA channels; each bit of this field offsets the

start Address of the respective WDMA channel.

Each bit is coded as follows:

0 = No offset

1 = Offset by 0x8000

Base address +0x34

DSPn_DMA_Config_3

21:16 DSPn_RDMA_CHANNEL_

OFFSET[5:0]

0x00

DSPn RDMA Channel Offset

There are six RDMA channels; each bit of this field offsets the

start Address of the respective RDMA channel.

Each bit is coded as follows:

0 = No offset

1 = Offset by 0x8000

5:0

DSPn_RDMA_CHANNEL_

ENABLE[5:0]

0x00

DSPn RDMA Channel Enable

There are six RDMA channels; each bit of this field enables the

respective RDMA channel.

Each bit is coded as follows:

0 = Disabled

1 = Enabled

Base address +0x36

DSPn_DMA_Config_4

0DSPn_DMA_WORD_SEL

DSPn Data Word Format

0 = Q3.20 format (4 integer bits, 20 fractional bits)

1 = Q0.23 format (1 integer bit, 23 fractional bits)

The data word format should be set according to the

requirements of the applicable DSP firmware.

Table 4-26. DMA Control (Cont.)

Bit

Label

Default

Description

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