CS47L35 datasheet(75/300 Pages) CIRRUS

75 / 300 page

DS1085F3

CS47L35

4.3 Digital Core

Figure 4-27. Isochronous Sample-Rate Converters (ISRCs)

The ISRC input control fields (see Fig. 4-27) are located at register addresses R2816–R2936 (0x0B00–0x0B78).

The full list of digital mixer control registers (R1600–R2936) is provided in Section 6. Generic register field definitions are

provided in Table 4-7.

The x_SRC fields select the input sources for the respective ISRC processing blocks. Note that the selected input sources

must be configured for the same sample rate as the ISRC to which they are connected.

The hexadecimal numbers in Fig. 4-27 indicate the corresponding x_SRC setting for selection of that signal as an input to

another digital-core function.

The ISRC paths should be kept disabled (ISRCn_INTm_ENA = 0, ISRCn_DECm_ENA = 0) if SYSCLK is not enabled.

The x_SRCn fields for all digital core functions should be held at 0x00 if SYSCLK is not enabled. SYSCLK must be present

and enabled before selecting other values for these fields. See Section 4.16.4 for further details (including requirements

for reconfiguring SYSCLK while digital core functions are enabled).

ISRCn_INT2_ENA

ISRCn_INT3_ENA

ISRCn_INT4_ENA

ISRCn_INT1_ENA

ISRCnINT1_SRC

ISRCnINT3_SRC

ISRCnINT4_SRC

ISRCnINT2_SRC

ISRC1 INT1 (A0h)

ISRC2 INT1 (A8h)

ISRC1 INT2 (A1h)

ISRC2 INT2 (A9h)

ISRC1 INT3 (A2h)

ISRC2 INT3 (AAh)

ISRC1 INT4 (A3h)

ISRC2 INT4 (ABh)

ISRCn_DEC2_ENA

ISRCn_DEC3_ENA

ISRCn_DEC4_ENA

ISRCn_DEC1_ENA

ISRCnDEC1_SRC

ISRCnDEC3_SRC

ISRCnDEC4_SRC

ISRCnDEC2_SRC

ISRC1 DEC1 (A4h)

ISRC2 DEC1 (ACh)

ISRC1 DEC2 (A5h)

ISRC2 DEC2 (ADh)

ISRC1 DEC3 (A6h)

ISRC2 DEC3 (AEh)

ISRC1 DEC4 (A7h)

ISRC2 DEC4 (AFh)

ISRCn_FSL

ISRCn_FSH

ISRC provides sample-rate conversions between synchronized sample rates on SYSCLK clock domain .

ISRCn_FSL identifies the lower of the two sample rates.

ISRCn_FSH identifies the higher of the two sample rates.

…

CS47L35 supports two ISRC blocks, i.e., n = 1 or 2

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