CS47L35 datasheet(188/300 Pages) CIRRUS

188 / 300 page

188

DS1085F3

CS47L35

4.16 Clocking and Sample Rates

There are some restrictions to be observed regarding the automatic sample-rate detection configuration, as noted in the

following:

• The same sample rate must not be selected on more than one of the SAMPLE_RATE_DETECT_n fields.

• Sample rates 192 kHz and 176.4 kHz must not be selected concurrently.

• Sample rates 96 kHz and 88.2 kHz must not be selected concurrently.

The control registers associated with the automatic sample-rate detection function are described in Table 4-93.

4.16.4 SYSCLK Control

The SYSCLK clock may be provided directly from external inputs (MCLK, or Slave Mode BCLK inputs). Alternatively,

SYSCLK can be derived using the integrated FLL, with MCLK, BCLK, LRCLK or SLIMCLK as a reference. The SYSCLK

must be configured and enabled before any audio path is enabled.

The SYSCLK frequency must be valid for all of the SAMPLE_RATE_n fields. It follows that all of the SAMPLE_RATE_n

fields must select numerically-related values, that is, all from the same group of sample rates as represented in Table 4-92.

SYSCLK_SRC is used to select the SYSCLK source, as described in Table 4-93. The source may be MCLKn, AIFnBCLK,

or FLL. If the FLL circuit is selected as the source, the FLL must be enabled and configured, as described in Section 4.16.9.

Note: If FLL1 is selected as SYSCLK source, the SYSCLK frequency is FVCO / 3. This enables SYSCLK frequencies of

98.304 MHz or 90.3168 MHz. See Section 4.16.9.

SYSCLK_FREQ and SYSCLK_FRAC must be set according to the frequency of the selected SYSCLK source.

The SYSCLK-referenced circuits within the digital core are clocked at a dynamically controlled rate that is limited by the

SYSCLK frequency. For maximum signal mixing and processing capacity, the highest possible SYSCLK frequency should

be used.

The SAMPLE_RATE_n fields are set according to the sample rates that are required by one or more of the CS47L35 audio

interfaces. The CS47L35 supports sample rates ranging from 8–192kHz.

The SYSCLK signal is enabled by setting SYSCLK_ENA. The applicable clock source (MCLKn, AIFnBCLK, or FLL) must

be enabled before setting SYSCLK_ENA. This bit must be cleared when reconfiguring the SYSCLK source or frequency.

The SYSCLK_ENA bit should also be cleared before stopping or removing the applicable clock source.

The SYSCLK signal is the reference clock for many different subsystems on the CS47L35. All of the SYSCLK-dependent

subsystems should be disabled if SYSCLK is not enabled. The SYSCLK_ENA bit must be set before enabling any

SYSCLK-dependent function, and all the dependent functions should be disabled before clearing the SYSCLK_ENA bit.

The SYSCLK-dependent subsystems are referenced below; if one or more of the following conditions is met, then the

SYSCLK signal is required, and should not be interrupted or reconfigured.

Table 4-92. SYSCLK Frequency Selection

SYSCLK Frequency (MHz)

SYSCLK_FREQ

SYSCLK_FRAC

Sample Rate (kHz)

SAMPLE_RATE_n

6.144

12.288

24.576

49.152

98.304

000

001

010

011

100

012

0x01

0x02

0x03

0x04

192

0x05

80x11

0x12

0x13

5.6448

11.2896

22.5792

45.1584

90.3168

000

001

010

011

100

111.025

0x09

22.05

0x0A

44.1

0x0B

88.2

0x0C

176.4

0x0D

Note: The SAMPLE_RATE_n fields must each be set to a value from the same group of sample rates, and from the same

group as the SYSCLK frequency.

CS47L35 датащи(PDF) 188 Page - Cirrus Logic

CS47L35 датащи(HTML) 188 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL