VSC8221 datasheet(17/138 Pages) MICROSEMI

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VSC8221

Data Sheet

VMDS-10106 Revision 4.1

December 2006

17 of 26

TXDiS/

SRESET

iPU

Transmit Disable or Software Reset.

When asserted, it places the PHY in a low power state, which includes disabling the

SerDes interface. Although the device is powered down, non-volatile Serial

Management interface registers retain their values.

TXDiS and SRESET are simply two names for the same function. The assertion

state (active high or low respectively) of this input pin is determined by the value of

Mii Register 21E.15 'SFP MODE' set at startup using Hardware Configuration or

using the EEPROM interface. Refer to “Hardware Configuration Using CMODE

pins,” page 53 and “EEPROM interface,” page 57 for details on configuration at

startup.

Table 5. System Clock interface Signals (SCi)

100

TFBGA

BALL

Signal Name

Type

Description

B10

XTAL1/

REFCLK

XTAL1 - Crystal Oscillator input.

Enabled by pulling OSCDiS (internal Oscillator Disabled) high, a 25MHz parallel

resonant crystal, with a +/- 50ppm frequency tolerance, should be connected

across XTAL1 and XTAL2. 33pf capacitors should be connected from XTAL1 and

XTAL2 to ground when using AT cut-type crystal rated for a parallel capacitance

of 20pf. PLLMODE should be left floating (or pulled low) on reset when a 25MHz

crystal is used.

REFCLK - PHY Reference Clock input.

The reference input clock can either be a 25MHz (PLLMODE is low) or 125MHz

(PLLMODE is high) reference clock, with a +/-100ppm frequency tolerance. See

EECLK / PLLMODE pin description for more details.

A10

XTAL2

Crystal Output.

25MHz parallel resonant crystal oscillator output. 33pF capacitors should be

connected from both XTAL1 and XTAL2 to ground when using AT cut-type crystal

rated for a parallel capacitance of 20pf. PLLMODE should be left floating (or tied

low) on reset when using the 25MHz crystal.

This output can be left floating if driving XTAL1/REFCLK with a reference clock.

H10

CLKOUTMi-

CRO/ OSCDiS

iPU/O

CLKOUTMiCRO - Clock Output.

This is a 4MHz (default) or a 125MHz output clock depending on the value of Mii

power supply.

OSCDiS - Active Low on-chip Oscillator Disable input.

This input is sampled during the device power-up sequence or on assertion of

RESET. When sampled high, the PHY enables the internal on-chip oscillator

allowing operation with a 25MHz crystal. When sampled low, the PHY’s oscillator

is turned off and the PHY must be supplied with an external 25MHz or 125MHz

clock on the REFCLK pin.

Table 4. Configuration and Control Signals (continued)

100 TFBGA

Ball

Signal Name

Type

Description

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