VSC8221 datasheet(22/138 Pages) MICROSEMI

22 / 138 page

VSC8221

Data Sheet

VMDS-10106 Revision 4.1

December 2006

22 of 26

Table 10. LED interface Signals

100

TFBGA

BALL

Signal Name

Type

Description

A4,A3,B3

LED2

LED1

LED0

OZC

LED - Direct-Drive LED Outputs.

After reset, these pins serve as the direct drive, low EMi, LED driver output pins.

All LEDs pins are active-low and driven at a 3.3V logic-high through the VDD33A

analog power supply. The function of each LED can be set using hardware

configuration or via Mii Register 27. Refer “Hardware Configuration Using

CMODE pins,” page 53 and Mii Register 27 for details.

Table 11. Serial MAC interface Signals

100

TFBGA

BALL

Signal

Name

Type

Description

K9,K10

TDP

TDN

iDiFF

Transmitter Data Differential input Pair.

Differential 1.25Gbaud receiver inputs with register selectable on-chip 100

Ω or 150Ω

differential termination. The TDP and TDN signals should be AC-coupled with external

0.01

µF series capacitors. See Section 9: “System Schematics” for further information.

K8,K7

RDP

RDN

ODiFF

Receiver Data Differential Output Pair.

Differential 1.25 Gbaud transmitter outputs. External 0.01

µF AC coupling capacitors

should be located on the PHY side. The register selectable 100

Ω or 150Ω differential

termination should be placed near the MAC side. For more information, see Section 9.1,

“System Schematic - SGMii/802.3z SerDes MAC to 1000Mbps CAT5 Media PHY

Operating Mode” on page 9-27. For more information on adjusting the output swing of

these pins, see “Register 17E (11h) - Serdes Control Register,” page 98.

J7,J8

SCLKP

SCLKN

ODiFF

SGMii Clock Differential Output Pair.

This signal pair is a differential 625MHz SGMii clock for the SGMii data in accordance

with Cisco’s SGMii specification. These pins should be AC-coupled with external 0.01

µF

series capacitors or left unconnected when not used. For more information, see Section

9.1, “System Schematic - SGMii/802.3z SerDes MAC to 1000Mbps CAT5 Media PHY

Operating Mode” on page 9-27. For more information on adjusting the output swing of

these pins, see “Register 17E (11h) - Serdes Control Register,” page 98.

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