VSC8221 datasheet(23/138 Pages) MICROSEMI

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VSC8221

Data Sheet

VMDS-10106 Revision 4.1

December 2006

23 of 26

RXLOS/

SiGDET

i/O

The functionality of this signal pin depends on the value of Mii Register 21E.15 ‘SFP

Mode’ which is set at startup. Refer to “Hardware Configuration Using CMODE pins,”

page 53 and “EEPROM interface,” page 57 for details on configuration at startup.

RXLOS - Receiver Loss of Signal Output (valid in SFP Mode, when Mii Register

21E.15 = 1).

This active high signal is asserted when the Cat-5 link goes down. The pulse width of the

RXLOS signal is configurable. Refer to Mii Register 30.1:0 for details.

SiGDET - SerDes Signal Detect (i/O) (valid in iEEE Mode, when Mii Register 21E.15

= 0).

SiGDET can be configured as an input or output and can be configured to function as

active low or active high at startup using hardware configuration or the EEPROM

interface. Refer to “Hardware Configuration Using CMODE pins,” page 53 or “EEPROM

interface,” page 57 for details on configuration at startup.

SiGDET as input:

When used as an input, the SiGDET signal is meant to be connected to the signal detect

output of the fiber optic transceiver. if SiGDET is high, this indicates receive activity on the

fiber optic transceiver.

if SiGDET is not used as an input, the PHY internally generates the signal detect function,

from the incoming data on the TDP and TDN signal pins.

SiGDET as Output:

For Serial MAC to CAT5 Media PHY Operating modes, SiGDET is asserted if a valid

CAT5 link has been established.

Table 11. Serial MAC interface Signals (continued)

100

TFBGA

BALL

Signal

Name

Type

Description

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