VSC8221 datasheet(18/138 Pages) MICROSEMI

18 / 138 page

VSC8221

Data Sheet

VMDS-10106 Revision 4.1

December 2006

18 of 26

MODDEF0/

CLKOUT

The functionality of this signal pin depends on the value for Mii Register 21E.15

‘SFP Mode’ which is set at startup. Refer to “Hardware Configuration Using

CMODE pins,” page 53, and “EEPROM interface,” page 57 for details on

configuration at startup.

MODDEF0 – Active Low PHY Ready indicator Output (valid in SFP Mode,

when Mii Register 21E.15 = 1).

This output is driven high immediately on PHY power-up or reset. This signal is

asserted low after the PHY startup sequence has completed and the PHY has

enabled access to the EEPROM connected to the EEPROM interface through the

Serial Management interface. The minimum time this signal is high before being

driven low is 10ms. The maximum time depends on the startup information stored

in the EEPROM. Refer to “PHY Startup and initialization,” page 61 and “EEPROM

interface,” page 57 for details.

CLKOUT – 125MHz Clock Output

(valid in iEEE Mode, when Mii Register 21E.15 = 0).

The PHY drives a 125MHz clock output after the PHY startup sequence has

completed. This clock can be disabled by clearing Mii Register 18.0. The voltage

levels of this clock are determined by the VDDiO power supply.

Table 6. Regulator Control and Analog Bias Signals

100 TFBGA

BALL

Signal Name

Type

Description

E10

REFREXT

ABiAS

REFREXT - Reference External Resistor.

Bias pin connects through external 2k

Ω (1%) resistor to analog ground.

F10

REFFiLT

ABiAS

REFFiLT - Reference Filter.

Filter internal reference through external 0.1

µF (10%) capacitor to analog ground.

C10

REGEN

ABiAS

REGEN- Regulator Enable.

Tie to VDD33A (3.3v) to enable the internal 1.2v regulator for normal chip

operation.

D10

REGOUT

ABiAS

REGOUT - Regulator Supply Output.

This is the output of the on-chip switching regulator, which generates the primary

1.2v power supply voltage VDD12. REGOUT must be connected to an off-chip

“LC” filter. See Section 9: “System Schematics” for more information.

Table 5. System Clock interface Signals (SCi) (continued)

100

TFBGA

BALL

Signal Name

Type

Description

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