VSC8221 datasheet(87/138 Pages) MICROSEMI

87 / 138 page

VSC8221

Data Sheet

VMDS-10106 Revision 4.1

December 2006

87 of 106

106

23.11:4 – Reserved

Writes to Mii Register 23 must preserve the value of bits 11:4, i.e., all writes to Mii Register 23 must be in the format xA2xh.

23.3 – Far End (Media-Side) Loopback Enable

When bit 23.3 is set to “1”, all incoming data from the link partner on the media interface is retransmitted back to the link partner

on the media interface. in addition, the incoming data will also appear on the RDP/RDN pins of the MAC interface. Any data

present on the TDP/TDN pins of the MAC interface is ignored by the VSC8221 when bit 23.3 is set. in order to avoid loss of

data, bit 23.3 should not be set while the VSC8221 is receiving data on the media interface. Bit 23.3 applies to all operating

modes of the VSC8221. When bit 23.3 is cleared, the VSC8221 resumes normal operation. This bit is cleared by default. Refer

to Section 17.3 on page 51.

23.0 – EEPROM Status

When bit 23.0 is set to “1”, an EEPROM has been detected on the external EEPROM interface. When cleared, bit 23.0 indicates

that no EEPROM has been detected.

23.2.25 Register 24 (18h) – PHY Control Register #2

24.15:13 – Reserved

These bits must always be written to as ‘111’.

24.12 - Enable PiCMG Miser Mode1

Setting bit 24.12 turns off some portions of the PHY's DSP block and reduces the PHY's Operating power. This bit can be set in

order to reduce power consumption in applications where the signal to noise ratio on the CAT-5 media is high, such as ethernet

over the backplane or where the cable length is short (<10m).

Bit

Name

Access

States

Reset

Value

Sticky

15:13 Reserved1

1 These bits must always be written to as ‘111’.

111

Enable PiCMG Miser Mode2

2 See Section 11 on page 32 for more information.

R/W

1 = PiCMG miser mode is enabled

0 = PiCMG miser mode is disabled

11:10 Reserved

9:7

TX FiFO Depth Control

R/W

000 to 010 = Reserved

011 = Jumbo packet mode

100 = iEEE mode

101 to 111 = Reserved

100

6:4

RX FiFO Depth Control

R/W

000 to 010 = Reserved

011 = Jumbo packet mode

100 = iEEE mode

101 to 111 = Reserved

100

3:1

Reserved

000

Connector Loopback

R/W

1 = Active (See Section 17.3 on page 51 for

details)

0 = Disable

1See Section 11 on page 32 for more information.

VSC8221 датащи(PDF) 87 Page - Microsemi Corporation

VSC8221 датащи(HTML) 87 Page - Microsemi Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL