VSC8221 datasheet(94/138 Pages) MICROSEMI

94 / 138 page

VSC8221

Data Sheet

VMDS-10106 Revision 4.1

December 2006

94 of 106

106

23.2.29 Register 28 (1Ch) – Auxiliary Control and Status Register

28.15 – Auto-Negotiation Complete

This bit is a copy of bit 1.5, duplicated here for convenience.

28.14 – Auto-Negotiation Disabled

When bit 28.14 is read as a “1”, this bit indicates that the auto-negotiation process has been disabled. This happens only when

28.13 – MDi/MDi-X Crossover indication

When bit 28.13 returns a “1”, the auto-negotiation state machine has determined that crossover does not exist in the signal path.

The crossover will therefore be performed internally to the PHY, as described by the MDi/MDi-X crossover specification.1

Bit

Name

Access

States

Reset

Value

Sticky

Auto-Negotiation Complete

1 = Auto-negotiation complete

0 = Auto-negotiation not complete

Auto-Negotiation Disabled

1 = Auto-negotiation was disabled

0 = Auto-negotiation is enabled

MDi/MDi-X Crossover indication

1 = MDi/MDi-X crossover detected

0 = MDi/MDi-X crossover not detected

CD Pair Swap

1 = CD pairs are swapped

0 = CD pairs are not swapped

A Polarity inversion

1 = Polarity swapped on pair A

0 = Polarity not swapped on pair A

B Polarity inversion

1 = Polarity swapped on pair B

0 = Polarity not swapped on pair B

C Polarity inversion

1 = Polarity swapped on pair C

0 = Polarity not swapped on pair C

D Polarity inversion

1 = Polarity swapped on pair D

0 = Polarity not swapped on pair D

Reserved

Enhanced ActiPHY Mode Enable

R/W

1 = Enable enhanced ActiPHY power manage-

ment

0 = Disable enhanced ActiPHY power manage-

ment

FDX Status

1 = Full Duplex

0 = Half Duplex

4:3

Speed Status

00 = Speed is 10BASE-T

01 = Speed is 100BASE-TX or 100BASE-FX

10 = Speed is 1000BASE-T

11 = Reserved

Reserved1

1 This bit must always be set to ‘1’.

1:0

Enhanced ActiPHYTM Sleep Timer

R/W

00=1 second

01=2 seconds

10-3 seconds

11=4 seconds

1This bit is valid only after descrambler lock has been achieved and as long as bit 18.5 is set to “0”.

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