VSC8221 datasheet(76/138 Pages) MICROSEMI

76 / 138 page

VSC8221

Data Sheet

VMDS-10106 Revision 4.1

December 2006

76 of 106

106

8.10:0 – LP Message/Unformatted Code

The Message/Unformatted Code bits indicate the message code being transmitted by the Link Partner.

23.2.10 Register 9 (09h) – 1000BASE-T Control Register

9.15:13 – Transmitter/Receiver Test Mode1

This test is valid only in 1000BASE-T mode. Refer to iEEE 802.3-2002, section 40.6.1.1.2 for more information.

• Test Mode 1: The PHY repeatedly transmits the following sequence of data symbols from all four transmitters: {{"+2"

followed by 127 "0" symbols}, {"-2" followed by 127 "0" symbols}, {"+1" followed by 127 "0" symbols}, {"-1" followed by

127 "0" symbols}, {128 "+2" symbols, 128 "-2" symbols, 128 "+2" symbols, 128 "-2" symbols}, {1024 "0" symbols}}. The

transmitter should use a 125.00 MHz ± 0.01% clock and should operate in MASTER timing mode.

Bit

Name

Acces

States

Reset Value

Sticky

15:13 Transmitter Test Mode

R/W

Described below, per iEEE 802.3, 40.6.1.1.2

000

MASTER/SLAVE Manual

Configuration Enable

R/W

1 = Enable MASTER/SLAVE Manual Configu-

ration value

0 = Disable MASTER/SLAVE Manual Configu-

ration value

MASTER/SLAVE Manual

Configuration Value

R/W

1 = Configure PHY as MASTER during MAS-

TER/SLAVE negotiation, only when bit 9.12 is

set to logical one.

0 = Configure PHY as SLAVE during MASTER/

SLAVE negotiation, only when bit 9.12 is set to

logical one.

Port Type

R/W

1 = Multi-port device

0 = Single-port device

1000BASE-T FDX Capability

R/W

1 = PHY is 1000BASE-T FDX capable

CMODE

1000BASE-T HDX Capability

R/W

1 = PHY is 1000BASE-T HDX capable

CMODE

7:0

Reserved

R/W

00000000

1The state of this register is internally latched when the auto-negotiation state machine enters the ABiLiTY_DETECT state. Changes to the

states of these bits are recognized only at that time. This register is valid only in 1000BASE-T mode.

Bit 1

(9.15)

Bit 2

(9.14)

Bit 3

(9.13)

Test Mode

Normal operation

Test Mode 1 – Transmit waveform test

Test Mode 2 – Transmit jitter test in MASTER mode

Test Mode 3 – Transmit jitter test in SLAVE mode

Test Mode 4 – Transmitter distortion test

Reserved; operation not defined

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