VSC8221 datasheet(45/138 Pages) MICROSEMI

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VSC8221

Data Sheet

VMDS-10106 Revision 4.1

December 2006

45 of 46

14.1 Supported instructions and instruction Codes

After a TAP reset, the Device identification Register is serially connected between TDi and TDO by default. The TAP instruction

Register is loaded either from a shift register (when a new instruction is shifted in), or, if there is no new instruction in the shift

instruction register, and the problem of toggling instruction bits during a shift is avoided. Unused codes are mapped to the

BYPASS instruction.

The VSC8221 supports the instruction codes listed in the following table and described below.

EXTEST

The mandatory EXTEST instruction allows testing of off-chip circuitry and board-level interconnections by sampling input pins

and loading data onto output pins. Outputs are driven by the contents of the boundary-scan cells, which have to be updated with

valid values (with the PRELOAD instruction) prior to the EXTEST instruction.1

SAMPLE/PRELOAD

The mandatory SAMPLE/PRELOAD instruction allows a snapshot of inputs and outputs during normal system operation to be

taken and examined. it also allows data values to be loaded into the boundary-scan cells prior to the selection of other

boundary-scan test instructions.

iDCODE

The optional iDCODE instruction provides the version number (bits 31:28), part number (bits 27:12), and Microsemi’s

manufacturer identity (bits 11:1) to be serially read from the PHY.

CLAMP

The optional CLAMP instruction allows the state of the signals driven from the component pins to be determined from the

Boundary-Scan Register while the Bypass Register is selected as the serial path between TDi and TDO. While the CLAMP

instruction is selected, the signals driven from the component pins will not change.1

HiGHZ

The optional HiGHZ instruction places the component in a state in which all of its system logic outputs are placed in a high

impedance state. in this state, an in-circuit test system may drive signals onto the connections normally driven by a component

output without incurring a risk of damage to the component. This makes it possible to use a board where not all of the

components are compatible with the iEEE 1149.1 standard.1

Table 24. JTAG interface instruction Codes

instruction

Code

Selected Register

Specification

EXTEST

0000

Boundary-Scan Register

Mandatory iEEE 1149.1

SAMPLE/PRELOAD

0001

Boundary-Scan Register

Mandatory iEEE 1149.1

iDCODE

0110

Device identification Register

Optional iEEE 1149.1

CLAMP

0010

Bypass Register

Optional iEEE 1149.1

HiGHZ

0011

Bypass Register

Optional iEEE 1149.1

BYPASS

0111

Bypass Register

Mandatory iEEE 1149.1

Reserved

0100, 1000,

1001, 1010,

1011, 1100,

1101,1110,

1111

1Following the use of this instruction, the on-chip system logic may be in an indeterminate state that will persist until a system reset is applied.

Therefore, the on-chip system logic may need to be reset on return to normal (i.e., non-test) operation.

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