VSC8221 datasheet(67/138 Pages) MICROSEMI

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VSC8221

Data Sheet

VMDS-10106 Revision 4.1

December 2006

67 of 106

106

23.2 Mii Register Descriptions

23.2.1 Register 0 (00h) – Mode Control Register

0.15 – Software Reset

Writing a “1” to bit 0.15 initiates a software reset. Once Software Reset is asserted, the PHY is returned to normal operating

mode and is ready for the next SMi transaction, so Software Reset always reads back “0”. Software Reset restores all SMi

registers to their default states, except for registers marked with an “S” or “SS” in the sticky column.

0.14 – Near End Loopback

When Near End Loopback is asserted, the Transmit Data (TXD) on the MAC interface is looped back as Receive Data (RXD). in

loopback mode, no signal is transmitted over the network media. The loopback mechanism works in all (10/100/1000) modes of

operation. The operating mode is determined by bits 0.13 and 0.6 (forced speed selection).

0.13, 0.6 – Forced Speed Selection

These bits determine the 10/100/1000 speed when auto-negotiation is disabled by clearing control bit 0.12. These bits are

ignored if control bit 0.12 is set. These bits also determine the operating mode when Near End Loopback (0.14) is set to “1”.

Bit

Name

Access

States

Reset Value

Sticky

Software Reset1

1 in MSA mode, when this bit is set, the PHY does not return the correct values for the subsequent register read operations. in order to read the correct PHY register

values, the station manager must provide 70 clock cycles on the MODDEF1/MDC pin or perform two byte read operations on any eeprom address other than in

page ‘110’ immediately following s/w reset.

R/W SC

1 = Reset asserted

0 = Reset de-asserted

Near End Loopback

R/W

1 = Loopback on

0 = Loopback off

6, 13 Forced Speed Selection

R/W

00 = 10Mbps

01 = 100Mbps

10 = 1000Mbps

11 = Reserved

Auto-Negotiation Enable

R/W

1 = Auto-negotiation enabled

0 = Auto-negotiation disabled

Power-Down2

2 The status of the Link Status bit, Mii Register 1.2, remains unchanged when this bit is set.

R/W

1 = Power-down

0 = Power-up

isolate

R/W

1 = Disable MAC outputs

0 = Normal Operation

Restart Auto-Negotiation

R/W SC

1 = Restart Mii

0 = Normal operation

Duplex Mode

R/W

1 = Full duplex

0 = Half duplex

Reserved

MSB for Speed Selection

(see bit 13 above)

See “Forced Speed Selection” Above

5:0

Reserved

000000

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