VSC8221 datasheet(55/138 Pages) MICROSEMI

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VSC8221

Data Sheet

VMDS-10106 Revision 4.1

December 2006

55 of 56

Auto-negotiation

Control[1]

CMODE3[0]

These CMODE bits set the default auto-negotiation advertisement

defaults by setting the defaults of Mii Registers 4 and 9.

10/100/1000BASE-T HDX, FDX

10/100BASE-T HDX, FDX

SFP Mode Disable

CMODE1[3]

This CMODE bit sets the default value of Mii Register 21E.15 .

This sets Mii Register 21E.15 = 1.

Sets the following PHY defaults:

• TXDiS/SRESET is active high i.e. behaves like TXDiS.

• MODDEF0/CLKOUT pin functions like MODDEF0 i.e this pin

is asserted low by the PHY once the EEPROM inter-

face is released for access through the SMi interface.

• RXLOS/SiGDET pins functions like the RXLOS.

• The SMi interface is set in MSA mode.

This sets Mii Register 21E.15 = 0.

Sets the following PHY defaults:

• TXDiS/SRESET is active low i.e. behaves like SRESET.

• MODDEF0/CLKOUT pin functions like CLKOUT i.e this pin

drive out a 125Mhz clock.

• RXLOS/SiGDET pin functions like the SiGDET.

• The SMi interface is set in iEEE mode

SiGDET pin direction

CMODE1[1]

The value of this bit is valid in non-SFP mode when CMODE bit

CMODE1[3] is 1. This CMODE bit set the direction of the SiGDET pin by

setting the default value of Extended Mii Register 19E.1

input

Output

SerDes Line

impedance

CMODE1[0]

Sets the internal end termination resistance value of the Serial MAC/

Media interface input pins.

050

Ω

175

Ω

SQE Enable

CMODE3[2]

Sets the default value of Mii Register 22.12.

0SQE Disabled (Mii Register 22.12=1)

SQE Enabled (Mii Register 22.12=0)

Table 27. PHY Operating Condition Parameter Description (continued)

PHY Operating

Condition Parame-

ter Name

CMODE Pin Name and

Bit Position

Value

Description

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