VSC8221 datasheet(83/138 Pages) MICROSEMI

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VSC8221

Data Sheet

VMDS-10106 Revision 4.1

December 2006

83 of 106

106

18.5 - Disable Automatic Pair Swap Correction

When set to ‘1’, the automatic pair swap correction feature of the PHY is disabled.

18.4 - Disable Polarity inversion

When set to ‘1’, the automatic polarity inversion feature of the PHY is disabled.

18.3 – Parallel-Detect Control

When bit 18.3 is “1”, Mii Register 4, bits [8:5], are taken into account when attempting to parallel-detect. This is the default

behavior expected by the standard. Setting 18.3 to a “0” will result in auto-negotiation ignoring the advertised abilities, as

specified in Mii Register 4, during parallel detection of a non-auto-negotiating 10BASE-T or 100BASE-TX PHY.

18.2 – Reserved

18.1 – Disable Automatic 1000BASE-T Next-Page Exchanges

Bit 18.1 is used to control the automatic exchange of 1000BASE-T Next-Pages defined in iEEE 802.3-2002 (Annex 40C). When

this bit is set, the automatic exchange of these pages is disabled, and the control is returned to the user through the SMi after

the base page has been exchanged. You then have the complete responsibility to both of the following:

• Send the correct sequence of Next-Pages to the Link Partner.

• Determine common capabilities and force the device into the correct configuration following successful exchange of

pages.

When bit 18.1 is reset to “0”, the 1000BASE-T related Next-Pages are automatically exchanged without user intervention. if the

Next Page bit 4.15 was set by the user in the Auto-Negotiation Advertisement register at the time the auto-negotiation was

restarted, control is returned to the user for additional Next-Pages following the 1000BASE-T Next-Page exchange.

if both bit 18.1 and Mii Register bit 4.15 are reset when an auto-negotiation sequence is initiated, all Next-Page exchange is

automatic, including sourcing of null pages. No user notification is provided until either auto-negotiation completes or fails. See

the description of Mii Register bit 4.15 for more details on standard Next-Page exchanges.

18.0 – CLKOUT Output Enable

When bit 18.0 is set to “1”, the VSC8221 provides a 125MHz clock on the CLKOUT output pin. The electrical specification for

this clock corresponds to the current settings for VDDiO. This clock is for use by the MAC, system manager CPU, or control

logic. By default, this pin is enabled, which enables the clock output independent of the status of any link, unless the hardware

reset is active (which also powers down the PLL). When disabled, the clock pins are normally driven low.

23.2.20 Register 19 (13h) – Reserved

19.15:0 - Reserved

Bit

Name

Access

States

Reset Value

Sticky

15:0

Reserved

00000000 00000000

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