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VSC8221 датащи(PDF) 35 Page - Microsemi Corporation |
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VSC8221 датащи(HTML) 35 Page - Microsemi Corporation |
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35 / 138 page ![]() VSC8221 Data Sheet VMDS-10106 Revision 4.1 December 2006 35 of 40 40 Figure 11. No Acknowledge (by Host) [N] 12.1.1 Write Operation - Random Write • R4..R0 are the 5 bits of the Register address R. • M7..M0 are bits of the Upper byte of the 16 bit Register data • L7..L0 are bits of the Upper byte of the 16 bit Register data The PHY register is written only after the host performs the lower data byte write operation. MODDEF1 1 9 8 START ACKNOWLEDGE MODDEF2 (Driven by Host) S 0 0 0 A 0 0 1 1 0 1 0 1 T A A R0 R1 R2 R3 R4 M0 M1 M2 M3 M4 M5 M6 M7 S 0 0 0 A 0 0 1 1 0 1 0 1 T A A R0 R1 R2 R3 R4 L0 L1 L2 L3 L4 L5 L6 L7 From Host to PHY/Receiver From PHY/Receiver to Host |
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