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VSC8221 датащи(PDF) 33 Page - Microsemi Corporation

номер детали VSC8221
подробное описание детали  Single Port 10/100/1000BASE-T PHY with1.25 Gbps SerDes for SFPs/GBICs
PDF  138 Pages
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производитель  MICROSEMI [Microsemi Corporation]
домашняя страница  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

VSC8221 датащи(HTML) 33 Page - Microsemi Corporation

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VSC8221
Data Sheet
VMDS-10106 Revision 4.1
December 2006
33 of 40
40
12 DUAL MODE SERIAL MANAGEMENT INTERFACE (SMI)
The Serial Management interface provides access to the PHY registers for device configuration and Status information. it also
provides access to the EEPROM connected to the EEDAT and EECLK pins (EEPROM interface) of the PHY. For details on
EEPROM access through the SMi interface, refer to Section 19 on page 57.
The MODDEF1/MDC, MODDEF2/MDiO, and MDiNT pins comprise the SMi interface.
By writing to Mii Register 21E.15 at startup (Refer to Section 18 on page 53 and Section 19 on page 57 for details), the SMi of
the PHY can be set to operate in one of the following two modes:
1.
MSA
2.
iEEE
12.1 PHY Register Access with SMi in MSA mode
in this mode, the PHY registers are accessed using the standard MSA compliant protocol. This protocol is generally used for
reading and writing to Atmel’s AT24 series compatible EEPROMs.
in this mode, the SMi pins function as follows:
According to the protocol described in the MSA specification, the following conditions are defined:
• Start [S]: A high to low transition on the MODDEF2 pin when MODDEF1 is high.
• Data [D]: A transition on the MODDEF2 pin when MODDEF1 is low. A low to high transition is '1' and a high to low
transition is '0'.
• Stop [T]: A low to high transition on the MODDEF2 pin when MODDEF1 is high.
• Acknowledge (By Receiver) [A]: A low driven by the PHY/Receiver after 8 Data states. The transition on MODDEF2
takes place when MODDEF1 is low. The host does not drive the MODDEF2 Data line in this condition.
• Acknowledge (By Host) [H]: A low driven by the host after 8 Data states. The transition on MODDEF2 takes place when
MODDEF1 is low. The PHY/Receiver does not drive the MODDEF2 Data line in this condition.
• No Acknowledge (By Host) [N]: A high driven by the host after 8 Data states. The transition on MODDEF2 takes place
when MODDEF1 is low. The PHY/Receiver does not drive the MODDEF2 Data line in this condition
Table 17. SMi Pin Descriptions - MSA Mode
Pin Name
Description
MODDEF1
Clock input. Connect to the SCL pin of the AT24 series of EEPROMs.
MODDEF2
Bidirectional Data. Connect to the SDA pin of the AT24 series of EEPROMs. This
pin should be pulled high on the board using a 4.7k
Ω to 10kΩ pullup resistor.
MDiNT
interrupt Signal.



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