VSC8221 datasheet(16/138 Pages) MICROSEMI

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VSC8221

Data Sheet

VMDS-10106 Revision 4.1

December 2006

16 of 26

8.4 Detailed Pin Descriptions

Digital Output

Standard digital output signal.

OZC

impedance Controlled Output

Ω integrated (on-chip) source series terminated, digital output signal. Used

primarily for timing-sensitive, 125MHz clock output pins, in addition to high speed

manufacturing test mode pins.

ODiFF

Differential Output Pair

SerDes differential output pair, with on-chip 100

Ω or 150Ω differential terminations.

Pins should be AC-coupled with external 0.01

µF capacitors.

i/O

Digital Bidirectional

Tristate-able, digital input and output signal.

iPU/O

Digital Bidirectional

Tristate-able, digital input and output signal. includes on-chip 100k pull-up to

VDDiO,VDDiOMiCRO,VDDiOCTRL or the VDD33A supply. Refer to

Section 15: “Power Supply and Associated Functional Signals” for details.

iPD/O

Digital Bidirectional

Tristate-able, digital input and output signal. includes on-chip 100k pull-down to

GND.

Digital Open Drain Output

Open drain digital output signal. Must be pulled to VDDiOMiCRO through an

external pull-up resistor.

ADiFF

Analog Differential

Analog differential signal pair for twisted pair interface.

ABiAS

Analog Bias

Analog bias or reference signal. Must be tied to external resistor and/or capacitor

bias network, as shown in Section 9: “System Schematics”.

Analog input

Analog input for sensing variable voltage levels.

Open Source

Open source digital output signal. Must be pulled to GND through an external pull-

down resistor.

Power Supply

Power supply connection. Must be connected to specified power supply plane.

GND

Ground Connection. Must be connected to ground.

No Connect

No connect signal. Must be left floating.

Table 4. Configuration and Control Signals

100 TFBGA

Ball

Signal Name

Type

Description

B4,C5,B5,A5

CMODE3

CMODE2

CMODE1

CMODE0

Hardware Chip Mode Select.

The CMODE inputs are used for hardware configuration of the various operating

modes of the PHY. Each pin has multiple settings, each of which is established by

an external 1% resistor tied to GND or VDD33A. See “Hardware Configuration

Using CMODE pins,” page 53 for details on configuring the PHY with the CMODE

pins.

RESET

Hardware Chip Reset.

RESET is an active low input. When asserted, it powers down all of the internal

reference voltages and the PLLs. it resets all internal logic, including the DSPs and

the Mii Management Registers.

Hardware reset is distinct from soft reset which only resets the port to accept new

configuration based on register settings.

Table 3. Signal Type Descriptions (continued)

Symbol

Signal Type

Description

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