VSC8221 datasheet(77/138 Pages) MICROSEMI

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VSC8221

Data Sheet

VMDS-10106 Revision 4.1

December 2006

77 of 106

106

• Test Mode 2: The PHY transmits the data symbol sequence {+2, -2} repeatedly on all channels. The transmitter should

use a 125.00 MHz ± 0.01% clock in the MASTER timing mode.

• Test Mode 3: The PHY transmits the data symbol sequence {+2, -2} repeatedly on all channels. The transmitter should

use a 125.00 MHz ± 0.01% clock and should operate in SLAVE timing mode.

• Test Mode 4: The PHY transmits the sequence of symbols generated by the following scrambler generator polynomial,

bit generation, and level mappings:

The maximum-length shift register used to generate the sequences defined by this polynomial is updated once per

symbol interval (8ns). The bits stored in the shift register delay line at a particular time n are denoted by Scrn[10:0]. At

each symbol period, the shift register is advanced by one bit, and one new bit represented by Scrn[0] is generated. Bits

Scr

n[8] and Scrn[10] are exclusive-OR'd together to generate the next Scrn[0] bit. The bit sequences, x0n, x1n, and x2n,

generated from combinations of the scrambler bits as shown in the following equations, shall be used to generate the

quinary symbols, s

n, as shown in the following table. The transmitter should use a 125.00 MHz ± 0.01% clock and should

operate in MASTER timing mode.

9.12 – MASTER/SLAVE Manual Configuration Enable1

When this bit is set to “0” (default), the MASTER/SLAVE designation of the local PHY is determined using the arbitration

protocol established in the iEEE Ethernet standard. When this bit is set to “1”, the MASTER/SLAVE designation of the local PHY

is set by bit 9.11. Note that MASTER/SLAVE configuration is valid only in 1000BASE-T mode.

9.11 – MASTER/SLAVE Configuration Value1

This bit is ignored when bit 9.12 is set to “0”. However, if bit 9.12 is set to “1”, bit 9.11 determines the MASTER/SLAVE

designation of the local PHY. if bit 9.12 is set to “1” and bit 9.11 set to “0” (default), the local PHY is forced to be a SLAVE. if bit

9.12 is set to “1” and bit 9.11 set to “1”, the local PHY is forced to be a MASTER. Note that MASTER/SLAVE configuration is

valid only in 1000BASE-T mode.

9.10 – Port Type1

Since the VSC8221 is a single port physical layer transceiver, bit 9.10 is set to “0” by default. When set to “0”, this bit indicates a

preference for operation as a SLAVE. if the Link Partner does not indicate the same preference, the local PHY will operate as a

SLAVE, and the Link Partner will be a MASTER. Otherwise, the normal MASTER/SLAVE assignment protocol is used.

Quinary Symbol, s

000

001

010

011

-1

100

101

110

-2

111

-1

1The state of this register is internally latched when the auto-negotiation state machine enters the ABiLiTY_DETECT state. Changes to the

states of these bits are recognized only at that time. This register is valid only in 1000BASE-T mode.

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