VSC8221 datasheet(11/138 Pages) MICROSEMI

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VSC8221

Data Sheet

VMDS-10106 Revision 4.1

December 2006

11 of 11

Figures

Figure 1.

VSC8221 Block Diagram........................................................................................................................................ 3

Figure 2.

100 Ball TFBGA Package Ball Diagram ............................................................................................................. 14

Figure 3.

Signal Type Descriptions ..................................................................................................................................... 15

Figure 4.

System Schematic - SGMii/802.3z SerDes MAC to 1000Mbps CAT5 Media PHY Operating Mode ............ 27

Figure 5.

System Schematic - 100Mbps Fiber Media implementation............................................................................. 28

Figure 6.

Twisted Pair interface........................................................................................................................................... 29

Figure 7.

Data Validity [D] .................................................................................................................................................... 34

Figure 8.

Start [S] and Stop [T] Definition ........................................................................................................................... 34

Figure 9.

Acknowledge (by Receiver) [A] ........................................................................................................................... 34

Figure 10.

Acknowledge (by Host) [H] .................................................................................................................................. 34

Figure 11.

No Acknowledge (by Host) [N] ............................................................................................................................ 35

Figure 12.

MDiO Read Frame............................................................................................................................................... 39

Figure 13.

MDiO Write Frame ............................................................................................................................................... 40

Figure 14.

Logical Representation of MDiNT Pin................................................................................................................. 40

Figure 15.

Test Access Port and Boundary Scan Architecture............................................................................................ 44

Figure 16.

Enhanced ActiPHY State Diagram...................................................................................................................... 47

Figure 17.

in-line Powered Ethernet Switch Diagram .......................................................................................................... 49

Figure 18.

Far-end Loopback Block Diagram ...................................................................................................................... 51

Figure 19.

Near-end Loopback Block Diagram.................................................................................................................... 52

Figure 20.

Connector Loopback............................................................................................................................................ 52

Figure 21.

EEPROM interface Connections......................................................................................................................... 58

Figure 22.

PHY Startup and initialization Sequence ............................................................................................................ 61

Figure 23.

Extended Page Register Diagram ...................................................................................................................... 63

Figure 24.

JTAG interface AC Timing................................................................................................................................... 118

Figure 25.

SMi AC Timing ..................................................................................................................................................... 119

Figure 26.

LED_CLK and LED_DATA Output AC Timing.................................................................................................. 120

Figure 27.

REFCLK AC Timing ........................................................................................................................................... 121

Figure 28.

CLKOUT AC Timing ........................................................................................................................................... 122

Figure 29.

CLKOUTMiCRO AC Timing .............................................................................................................................. 122

Figure 30.

RESET AC Timing.............................................................................................................................................. 123

Figure 31.

100-Ball 9 × 9mm TFBGA Mechanical Specification ....................................................................................... 124

Figure 32.

SGMii Rx Path from the PHY to the MAC ........................................................................................................ 127

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