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VSC8221 датащи(PDF) 88 Page - Microsemi Corporation

номер детали VSC8221
подробное описание детали  Single Port 10/100/1000BASE-T PHY with1.25 Gbps SerDes for SFPs/GBICs
PDF  138 Pages
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производитель  MICROSEMI [Microsemi Corporation]
домашняя страница  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

VSC8221 датащи(HTML) 88 Page - Microsemi Corporation

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VSC8221
Data Sheet
VMDS-10106 Revision 4.1
December 2006
88 of 106
106
24.11:10 - Reserved
24.9:7 – TX FiFO Depth Control1
Bits 24.9:7 control symbol buffering for the transmit synchronization FiFO used in all 1000BT modes. An internal FiFO is used to
synchronize the clock domains between the MAC transmit clock and the PHY’s clock (e.g., REFCLK), used to transmit symbols
on the local PHY’s twisted pair interface.
The iEEE mode supports up to 1518-byte packet size with the minimum inter-packet gap (iPG). The jumbo packet mode adds
latency to the path to support up to 9600-byte packets with the minimum inter-packet gap (iPG). When using jumbo packet
mode, a larger iPG is recommended due to the possible compression of the iPG at the output of the FiFO.
24.6:4 – RX FiFO Depth Control1
Used in 1000BT , bits 24.6:4 control symbol buffering as determined by the receive synchronization FiFO. An internal FiFO is
used to synchronize the clock domains between the MAC receive clock and the PHY’s clock (e.g., REFCLK), used to receive
symbols on the local PHY’s twisted pair interface.
The iEEE mode supports up to 1518-byte packet size with the minimum inter-packet gap (iPG). The jumbo packet mode adds
latency to the path to support up to 9600-byte packets with the minimum inter-packet gap (iPG). When using jumbo packet
mode, a larger iPG is recommended due to the possible compression of the iPG at the output of the FiFO.
24.3:1 – Reserved
24.0 - Connector Loopback
See Section 17.3 on page 51 for details.
23.2.26 Register 25 (19h) – interrupt Mask Register
1The TX and RX FiFOs are not used for 10BASE-T and 100BASE-TX.
Register 25 (19h) – interrupt Mask Register
Bit
Name
Access States
Reset
Value
Sticky
15
interrupt Pin Enable
R/W
1 = Enable interrupt pin
0 = Disable interrupt pin
0
S
14
Reserved
RO
0
13
Link State-Change interrupt Mask
R/W
1 = Enable Link State/ Energy Detect interrupt
0 = Disable Link State/ Energy Detect interrupt
0
S
12
Reserved
RO
0
11
Auto-Negotiation Error interrupt
Mask
R/W
1 = Enable Auto-Negotiation Error interrupt
0 = Disable Auto-Negotiation Error interrupt
0
S
10
Auto-Negotiation-Done / interlock
Done interrupt Mask
R/W
1 = Enable Auto-Negotiation-Done/ interlock Done
interrupt
0 = Disable Auto-Negotiation-Done/ interlock
Done interrupt
0
S
9
inline Powered Device Detected
interrupt Mask
R/W
1 = Enable inline Powered Device Detected inter-
rupt
0 = Disable inline Powered Device Detected inter-
rupt
0
S
8
Symbol Error interrupt Mask
R/W
1 = Enable Symbol Error interrupt
0 = Disable Symbol Error interrupt
0
S
7
Descrambler Lock-Lost interrupt
Mask
R/W
1 = Enable Lock-Lost interrupt
0 = Disable Lock-Lost interrupt
0
S



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