VSC8221 datasheet(19/138 Pages) MICROSEMI

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VSC8221

Data Sheet

VMDS-10106 Revision 4.1

December 2006

19 of 26

Table 7. JTAG Access Port

100 TFBGA

BALL

Signal Name

Type

Description

TDi

iPU5V

JTAG Test Data Serial input Data.

Serial test pattern data is scanned into the device on this input pin, which is

sampled with respect to the rising edge of TCK.

This pin should be tied high to VDDiOCTRL in designs that do not require JTAG

functionality.

TDO

OZC

JTAG Test Data Serial Output Data.

Serial test data from the PHY is driven out of the device on the falling edge of

TCK. This pin should be left floating during normal chip operation.

TMS

iPU5V

JTAG Test Mode Select.

This input pin, sampled on the rising edge of TCK, controls the TAP (Test Access

Port) controller’s 16-state, instruction state machine.

This pin should be tied high to VDDiOCTRL in designs that do not require JTAG

functionality.

TCK

iPU5V

JTAG Test Clock.

This input pin is the master clock source used to control all JTAG test logic in the

device.

This pin should be pulled down with a 2k

Ω pull-down resistor in designs that

require JTAG functionality.

This pin should be tied low in designs that do not require JTAG functionality.

TRST

iPU5V

JTAG Reset.

This active low input pin serves as an asynchronous reset to the JTAG TAP

controller’s state machine. As required by the JTAG standard, this pin includes an

integrated on-chip pull-up (to VDDiOCTRL) resistor. Because of the internal

pull-up, if the JTAG controller on the printed circuit board does not utilize the

TRST signal, then the device will still function correctly when the TRST pin is left

unconnected on the board.

if the JTAG port of the PHY is not used on the printed circuit board, then this pin

should be pulled down with a 2k

Ω pull-down resistor or a falling edge must be

provided to this pin after PHY power up.

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