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VSC8221 датащи(PDF) 44 Page - Microsemi Corporation |
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VSC8221 датащи(HTML) 44 Page - Microsemi Corporation |
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44 / 138 page ![]() VSC8221 Data Sheet VMDS-10106 Revision 4.1 December 2006 44 of 46 46 14 TEST MODE INTERFACE (JTAG) The PHY supports the Test Access Port and Boundary Scan Architecture iEEE 1149.1 standards. The device includes an iEEE 1149.1 compliant test interface, often referred to as a “JTAG TAP interface”. iEEE 1149.1 defined test logic provides the following standardized test methodologies: • Testing the interconnections between integrated circuits once they have been assembled onto a printed circuit board or other substrate. • Testing the integrated circuit itself during iC and systems manufacture. • Observing or modifying circuit activity during the component’s normal operation. The JTAG Test interface logic on the PHY, accessed through a Test Access Port (TAP) interface, consists of a boundary- scan register and other logic control blocks. The TAP controller includes all iEEE-required signals (TMS, TCK, TDi, and TDO), in addition to the optional asynchronous reset signal TRST. The following figure diagrams the TAP and Boundary Scan Architecture. Figure 15. Test Access Port and Boundary Scan Architecture The PHY also includes the optional Device identification Register, shown in the following table, which allows the manufacturer, part number, and version number of the device to be determined through the TAP Controller. See Chapter 11 of the iEEE 1149.1-1990 specifications for more details. Also, note that some of the information in the identification register is duplicated in the iEEE-specified bit fields in Mii Register 3 (PHY identifier Register #2). Table 23. JTAG Device identification Register Description Description Device Version Number (or Revision Code) Part Number (or Model Number) Microsemi’s Manufacturer identity LSB Bit Field 31 - 28 27 - 12 11 - 1 0 Binary Value 0001 1000 0010 0010 0001 001 1001 1000 1 Boundary-Scan Register Device Identification Register Bypass Register Instruction Register, Instruction Decode, Control Test Access Port Controller TRSTz TMS TDI TCK select control tdoenable control Mux, DFF TDO |
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