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SuperI/O Module (Continued)

Alarm Interrupt. This interrupt is generated immediately after a time update in which the seconds, minutes, hours, date and

month time equal their respective alarm counterparts. It is cleared to 0 as long as bit 7 of the CRD Register is reads 0.

0: Disable.

1: Enable.

Update Ended Interrupt. This interrupt is generated when an update occurs. It is cleared to 0 on RTC reset (i.e., hardware

or software reset) or when the RTC is disable.

0: Disable.

1: Enable.

Reserved. This bit is defined as “Square Wave Enable” by the MC146818 and is not supported by the RTC. This bit is

always read as 0.

Data Mode. This bit is reset at VPP power-up reset only.

0: Enable BCD format.

1: Enable Binary format.

Hour Mode. This bit is reset at VPP power-up reset only.

0: Enable 12-hour format.

1: Enable 24-hour format.

Daylight Saving. This bit is reset at VPP power-up reset only.

0: Disable.

1: Enable:

- In the spring, time advances from1:59:59 AM to 3:00:00 AM on the first Sunday in April.

- In the fall, time returns from 1:59:59 AM to 1:00:00 AM on the last Sunday in October.

Index 0Ch

RTC Control Register C - CRC (RO)

Reset Type: Bit Specific

IRQ Flag. Mirrors the value on the interrupt output signal. When interrupt is active, IRQF is 1. To clear this bit (and deacti-

vate the interrupt pin), read the CRC Register as the flag bits UF, AF and PF are cleared after reading this register.

0: IRQ inactive.

1: Logic equation is true: ((UIE and UF) or (AIE and AF) or (PIE and PF)).

Periodic Interrupt Flag. Cleared to 0 on RTC reset (i.e., hardware or software reset) or the RTC disabled. In addition, this

bit is cleared to 0 when this register is read.

0: No transition occurred on the selected tap since the last read.

1: Transition occurred on the selected tap of the divider chain.

Alarm Interrupt Flag. Cleared to 0 as long as bit 7 of the CRD Register is reads 0. In addition, this bit is cleared to 0 when

this register is read.

0: No alarm detected since the last read.

1: Alarm condition detected.

Update Ended Interrupt Flag. Cleared to 0 on RTC reset (i.e., hardware or software reset) or the RTC disabled. In addition,

this bit is cleared to 0 when this register is read.

0: No update occurred since the last read.

1: Time registers updated.

3:0

Reserved.

Index 0Dh

RTC Control Register D - CRD (RO)

Reset Type: VPP PUR

Valid RAM and Time. This bit senses the voltage that feeds the RTC (VSB or VBAT) and indicates whether or not it was too

low since the last time this bit was read. If it was too low, the RTC contents (time/calendar registers and CMOS RAM) is not

valid.

0: The voltage that feeds the RTC was too low.

1: RTC contents (time/calendar registers and CMOS RAM) are valid.

6:0

Reserved.

Index Programmable

Date of Month Alarm Register - DOMA (R/W)

Reset Type: VPP PUR

7:0

Date of Month Alarm Data. Values may be 01 to 31 in BCD format or 01 to 1F in Binary format.

When bits 7 and 6 are both set to one (“11”), unconditional match is selected. (Default)

Table 4-20. RTC Registers (Continued)

Bit

Description

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