TMS320LC2401AVFS datasheet(111/134 Pages) TI

111 / 134 page

TMS320LF2407A,TMS320LF2406A, TMS320LF2403A, TMS320LF2402A

TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

111

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

migrating from 240x devices to 240xA devices

This section highlights the new features/migration issues of the 240xA devices (as compared to the 240x family)

and describes the impact these features/issues have on user applications.

maximum clock speed

240xA devices can operate at a maximum speed of 40 MHz compared to the 30-MHz operation of 240x devices.

This change in clock speed warrants a change in the register contents of all the peripherals. For example, to

maintain the same baud rate, the divisor values that are loaded to the SPI, SCI, and CAN registers must be

recalculated.

code security module

240xA devices incorporate a “code security module” which protects the contents of program memory from

unauthorized duplication. Passwords stored in password locations (PWL) 0040h to 0043h are used for this

purpose. Even if the code is not secured with passwords (i.e., PWL contains FFFFFFFFFFFFFFFFh), the PWL

must still be read to gain access to the program memory contents. Note that locations 0040h to 0043h were

available for user code in the 240x devices, which lack the “code security module”. In 240xA devices, these

locations are reserved for the passwords and are not available for the user code. Even if code security feature

is not used, these locations must be written with all ones. This fact must be borne in mind while submitting ROM

codes to TI.

input-qualifier circuitry

An input-qualifier circuitry qualifies the input signal to the CAP1–6 (QEP1−4), XINT1/2, ADCSOC, and

PDPINTA/B pins in the x240xA devices. The state of the internal input signal will change only after these pins

are high/low for 6 (12) clock edges. The user must hold the pin high/low for 6 (12) cycles to ensure that the device

see the level change. The increase in the pulse width of the signals used to excite these pins must be taken

into account while migrating from the 240x to the 240xA family.

Bit 6 of the SCSR2 register controls whether 6 clock edges (bit 6 = 0) or 12 clock edges (bit 6 = 1) are used

to block 5- or 11-cycle glitches. This bit is a “reserved” bit in 240x devices.

status of the PDPINTx pin

The current status of the PDPINTx pins is now reflected in bit 8 of the COMCONx registers. This bit is a

“reserved” bit in 240x devices.

operation of the IOPC0 pin

At reset, all LF240xA devices come up with the W/R/IOPC0 pin in W/R mode. On devices that lack an external

memory interface (e.g., LF2406A), W/R mode is not functional and MCRB.0 must be set to a 0 if the IOPC0

pin is to be used. The XMIF Hi-Z control bit (bit 4 of the SCSR2 register) is reserved in these devices and must

be written with a zero.

external pulldown resistor for TRST pin

An external pulldown resistor may be needed for the TRST pin in boards that operate in noisy environments.

Refer to the TRST pin description for more details.

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