TMS320LC2401AVFS datasheet(89/134 Pages) TI

89 / 134 page

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A

TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

interrupt timing

INT refers to XINT1 and XINT2. PDP refers to PDPINTx.

switching characteristics over recommended operating conditions (see Figure 38)

PARAMETER

MIN

MAX

UNIT

t ()

Delay time, PDPINTA low to PWM

if bit 6 of SCSR2 = 0

(6 + 1)tc(CO) + 12†

td(PDP-PWM)HZ

Delay time, PDPINTA low to PWM

high-impedance state

if bit 6 of SCSR2 = 1

(12+ 1)tc(CO) + 12†

td(INT)

Delay time, INT low/high to interrupt-vector

fetch

10tc(CO) + tW (INT)

† Includes i/p qualifier cycles plus synchronization plus propagation delay

timing requirements (see Figure 38)

MIN

MAX

UNIT

†

Pulse duration INT input low/high

if bit 6 of SCSR2 = 0

6tc(CO)

tw(INT)†

Pulse duration, INT input low/high

if bit 6 of SCSR2 = 1

12tc(CO)

†

Pulse duration PDPINTx input low

if bit 6 of SCSR2 = 0

6tc(CO)

tw(PDP)†

Pulse duration, PDPINTx input low

if bit 6 of SCSR2 = 1

12tc(CO)

† This is different from 240x devices.

PWM†

PDPINTx

CLKOUT

tw(PDP)

td(PDP-PWM)HZ

XINT1, XINT2

tw(INT)

Interrupt Vector

td(INT)

† PWM refers to all the PWM pins in the device (i.e., PWMn and TnPWM pins). The state of the PWM pins after PDPINTx is taken

high depends on the state of the FCOMPOE bit.

A0−A15

Figure 38. External Interrupts Timing

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