TMS320LC2401AVFS datasheet(87/134 Pages) TI

87 / 134 page

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A

TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

TIMING EVENT MANAGER INTERFACE

PWM timing

PWM refers to all PWM outputs on EVA and EVB.

switching characteristics over recommended operating conditions for PWM timing

[H = 0.5tc(CO)] (see Figure 35)

PARAMETER

MIN

MAX

UNIT

tw(PWM)†

Pulse duration, PWMx output high/low

2H+5

td(PWM)CO

Delay time, CLKOUT low to PWMx output switching

† PWM outputs may be 100%, 0%, or increments of tc(CO) with respect to the PWM period.

timing requirements‡ [H = 0.5tc(CO)] (see Figure 36)

MIN

MAX

UNIT

tw(TMRDIR)

Pulse duration, TMRDIR low/high

4H+5

tw(TMRCLK)

Pulse duration, TMRCLK low as a percentage of TMRCLK cycle time

twh(TMRCLK)

Pulse duration, TMRCLK high as a percentage of TMRCLK cycle time

tc(TMRCLK)

Cycle time, TMRCLK

tc(CO)

‡ Parameter TMRDIR is equal to the pin TDIRx, and parameter TMRCLK is equal to the pin TCLKINx.

tw(PWM)

td(PWM)CO

PWMx

CLKOUT

Figure 35. PWM Output Timing

CLKOUT

tw(TMRDIR)

TMRDIR†

† Parameter TMRDIR is equal to the pin TDIRx.

Figure 36. TMRDIR Timing

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