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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320LC2401AVFS датащи(PDF) 97 Page - Texas Instruments |
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TMS320LC2401AVFS датащи(HTML) 97 Page - Texas Instruments |
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97 / 134 page  TMS320LF2407A,TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145K − JULY 2000 − REVISED AUGUST 2005 97 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SPI slave mode timing parameters (continued) SPI slave mode external timing parameters (clock phase = 1)†‡ (see Figure 44) NO. MIN MAX UNIT 12 tc(SPC)S Cycle time, SPICLK 8tc(CO) ns 13§ tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S−10 0.5tc(SPC)S ns 13§ tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S−10 0.5tc(SPC)S ns 14§ tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)S−10 0.5tc(SPC)S ns 14§ tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)S−10 0.5tc(SPC)S ns 17§ tsu(SOMI-SPCH)S Setup time, SPISOMI before SPICLK high (clock polarity = 0) 0.125tc(SPC)S ns 17§ tsu(SOMI-SPCL)S Setup time, SPISOMI before SPICLK low (clock polarity = 1) 0.125tc(SPC)S ns 18§ tv(SPCH-SOMI)S Valid time, SPISOMI data valid after SPICLK high (clock polarity =0) 0.75tc(SPC)S ns 18§ tv(SPCL-SOMI)S Valid time, SPISOMI data valid after SPICLK low (clock polarity =1) 0.75tc(SPC)S ns 21§ tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 0) 0 ns 21§ tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 1) 0 ns 22§ tv(SPCH-SIMO)S Valid time, SPISIMO data valid after SPICLK high (clock polarity = 0) 0.5tc(SPC)S ns 22§ tv(SPCL-SIMO)S Valid time, SPISIMO data valid after SPICLK low (clock polarity = 1) 0.5tc(SPC)S ns † The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is set. ‡ tc = system clock cycle time = 1/CLKOUT = tc(CO) § The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). |
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