TMS320LC2401AVFS datasheet(34/134 Pages) TI

34 / 134 page

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

DSP CPU core

The TMS320x240xA devices use an advanced Harvard-type architecture that maximizes processing power by

maintaining two separate memory bus structures — program and data — for full-speed execution. This multiple

bus structure allows data and instructions to be read simultaneously. Instructions support data transfers

between program memory and data memory. This architecture permits coefficients that are stored in program

memory to be read in RAM, thereby eliminating the need for a separate coefficient ROM. This, coupled with a

four-deep pipeline, allows the LF240xA/LC240xA devices to execute most instructions in a single cycle. See

the functional block diagram of the 240xA DSP CPU for more information.

TMS320x240xA instruction set

The x240xA microprocessor implements a comprehensive instruction set that supports both numeric-intensive

signal-processing operations and general-purpose applications, such as multiprocessing and high-speed

control.

For maximum throughput, the next instruction is prefetched while the current one is being executed. Because

the same data lines are used to communicate to external data, program, or I/O space, the number of cycles an

instruction requires to execute varies, depending upon whether the next data operand fetch is from internal or

external memory. Highest throughput is achieved by maintaining data memory on chip and using either internal

or fast external program memory.

addressing modes

The TMS320x240xA instruction set provides four basic memory-addressing modes: direct, indirect, immediate,

and register.

In direct addressing, the instruction word contains the lower seven bits of the data memory address. This field

is concatenated with the nine bits of the data memory page pointer (DP) to form the 16-bit data memory address.

Therefore, in the direct-addressing mode, data memory is paged effectively with a total of 512 pages, with each

page containing 128 words.

Indirect addressing accesses data memory through the auxiliary registers. In this addressing mode, the address

of the instruction operand is contained in the currently selected auxiliary register. Eight auxiliary registers

(AR0−AR7) provide flexible and powerful indirect addressing. To select a specific auxiliary register, the auxiliary

scan-based emulation

TMS320x2xx devices incorporate scan-based emulation logic for code-development and hardware-

development support. Scan-based emulation allows the emulator to control the processor in the system without

the use of intrusive cables to the full pinout of the device. The scan-based emulator communicates with the x2xx

by way of the IEEE 1149.1-compatible (JTAG) interface. The x240xA DSPs do not include boundary scan. The

scan chain of these devices is useful for emulation function only.

TMS320LC2401AVFS датащи(PDF) 34 Page - Texas Instruments