TMS320LC2401AVFS datasheet(48/134 Pages) TI

48 / 134 page

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PWM characteristics

Characteristics of the PWMs are as follows:

D 16-bit registers

D Programmable deadband for the PWM output pairs, from 0 to 12 µs

D Minimum deadband width of 25 ns

D Change of the PWM carrier frequency for PWM frequency wobbling as needed

D Change of the PWM pulse widths within and after each PWM period as needed

D External-maskable power and drive-protection interrupts

D Pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space

vector PWM waveforms

D Minimized CPU overhead using auto-reload of the compare and period registers

D The PWM pins are driven to a high-impedance state when the PDPINTx pin is driven low and after PDPINTx

signal qualification. The PDPINTx pin (after qualification) is reflected in bit 8 of the COMCONx register.

−

PDPINTA pin status is reflected in bit 8 of COMCONA register.

−

PDPINTB pin status is reflected in bit 8 of COMCONB register.

capture unit

The capture unit provides a logging function for different events or transitions. The values of the selected GP

timer counter is captured and stored in the two-level-deep FIFO stacks when selected transitions are detected

on capture input pins, CAPx (x = 1, 2, or 3 for EVA; and x = 4, 5, or 6 for EVB). The capture unit consists of three

capture circuits.

Capture units include the following features:

D One 16-bit capture control register, CAPCONx (R/W)

D One 16-bit capture FIFO status register, CAPFIFOx

D Selection of GP timer 1/2 (for EVA) or 3/4 (for EVB) as the time base

D Three 16-bit 2-level-deep FIFO stacks, one for each capture unit

D Three capture input pins (CAP1/2/3 for EVA, CAP4/5/6 for EVB)—one input pin per capture unit. [All inputs

are synchronized with the device (CPU) clock. In order for a transition to be captured, the input must hold

at its current level to meet two rising edges of the device clock. The input pins CAP1/2 and CAP4/5 can also

be used as QEP inputs to the QEP circuit.]

D User-specified transition (rising edge, falling edge, or both edges) detection

D Three maskable interrupt flags, one for each capture unit

quadrature-encoder pulse (QEP) circuit

Two capture inputs (CAP1 and CAP2 for EVA; CAP4 and CAP5 for EVB) can be used to interface the on-chip

QEP circuit with a quadrature encoder pulse. Full synchronization of these inputs is performed on-chip.

Direction or leading-quadrature pulse sequence is detected, and GP timer 2/4 is incremented or decremented

by the rising and falling edges of the two input signals (four times the frequency of either input pulse).

TMS320LC2401AVFS датащи(PDF) 48 Page - Texas Instruments

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