TMS320LC2401AVFS datasheet(38/134 Pages) TI

38 / 134 page

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

status and control registers (continued)

Table 5. Status Register Field Definitions (Continued)

FIELD

FUNCTION

Data memory page pointer. The 9-bit DP register is concatenated with the 7 LSBs of an instruction word to form a direct memory

address of 16 bits. DP can be modified by the LST and LDP instructions.

INTM

Interrupt mode bit. When INTM is set to 0, all unmasked interrupts are enabled. When set to 1, all maskable interrupts are disabled.

INTM is set and reset by the SETC INTM and CLRC INTM instructions. RS also sets INTM. INTM has no effect on the unmaskable

RS and NMI interrupts. Note that INTM is unaffected by the LST instruction. This bit is set to 1 by reset. It is also set to 1 when

a maskable interrupt trap is taken.

Overflow flag bit. As a latched overflow signal, OV is set to 1 when overflow occurs in the arithmetic logic unit (ALU). Once an

overflow occurs, the OV remains set until a reset, BCND/D on OV/NOV, or LST instruction clears OV.

OVM

Overflow mode bit. When OVM is set to 0, overflowed results overflow normally in the accumulator. When set to 1, the accumulator

is set to either its most positive or negative value upon encountering an overflow. The SETC and CLRC instructions set and reset

this bit, respectively. LST can also be used to modify the OVM.

Product shift mode. If these two bits are 00, the multiplier’s 32-bit product is loaded into the ALU with no shift. If PM = 01, the PREG

output is left-shifted one place and loaded into the ALU, with the LSB zero-filled. If PM = 10, the PREG output is left-shifted by 4 bits

and loaded into the ALU, with the LSBs zero-filled. PM = 11 produces a right shift of 6 bits, sign-extended. Note that the PREG

contents remain unchanged. The shift takes place when transferring the contents of the PREG to the ALU. PM is loaded by the

SPM and LST #1 instructions. PM is cleared by RS.

SXM

Sign-extension mode bit. SXM = 1 produces sign extension on data as it is passed into the accumulator through the scaling shifter.

SXM = 0 suppresses sign extension. SXM does not affect the definitions of certain instructions; for example, the ADDS instruction

suppresses sign extension regardless of SXM. SXM is set by the SETC SXM instruction and reset by the CLRC SXM instruction

and can be loaded by the LST #1 instruction. SXM is set to 1 by reset.

Test/control flag bit. TC is affected by the BIT, BITT, CMPR, LST #1, and NORM instructions. TC is set to a 1 if a bit tested by BIT

or BITT is a 1, if a compare condition tested by CMPR exists between AR (ARP) and AR0, if the exclusive-OR function of the 2 most

significant bits (MSBs) of the accumulator is true when tested by a NORM instruction. The conditional branch, call, and return

instructions can execute based on the condition of TC.

XF pin status bit. XF indicates the state of the XF pin, a general-purpose output pin. XF is set by the SETC XF instruction and reset

by the CLRC XF instruction. XF is set to 1 by reset.

central processing unit

The TMS320x240xA central processing unit (CPU) contains a 16-bit scaling shifter, a 16 x 16-bit parallel

multiplier, a 32-bit central arithmetic logic unit (CALU), a 32-bit accumulator, and additional shifters at the

outputs of both the accumulator and the multiplier. This section describes the CPU components and their

functions. The functional block diagram shows the components of the CPU.

input scaling shifter

The TMS320x240xA provides a scaling shifter with a 16-bit input connected to the data bus and a 32-bit output

connected to the CALU. This shifter operates as part of the path of data coming from program or data space

to the CALU and requires no cycle overhead. It is used to align the 16-bit data coming from memory to the 32-bit

CALU. This is necessary for scaling arithmetic as well as aligning masks for logical operations.

The scaling shifter produces a left shift of 0 to 16 on the input data. The LSBs of the output are filled with zeros;

the MSBs can either be filled with zeros or sign-extended, depending upon the value of the SXM bit

(sign-extension mode) of status register ST1. The shift count is specified by a constant embedded in the

instruction word or by a value in TREG. The shift count in the instruction allows for specific scaling or alignment

operations specific to that point in the code. The TREG base shift allows the scaling factor to be adaptable to

the system’s performance.

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