TMS320LC2401AVFS datasheet(109/134 Pages) TI

109 / 134 page

TMS320LF2407A,TMS320LF2406A, TMS320LF2403A, TMS320LF2402A

TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

109

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

10-bit analog-to-digital converter (ADC) (continued)

internal ADC module timing† (see Figure 51)

MIN

MAX

UNIT

C l ti

ADC

l d l k

33 3

tc(AD)

Cycle time, ADC prescaled clock

33.3

Pulse duration total sample/hold and

tw(SHC)

Pulse duration, total sample/hold and

‡

500

tw(SHC)

conversion time‡

500

td(SOC-SH)

Delay time, start of conversion to beginning of sample and hold

2tc(CO)

tw(SH)

Pulse duration, sample and hold time

2tc(AD)§

32tc(AD)

tw(C)

Pulse duration, total conversion time

10tc(AD)

td(EOC)

Delay time, end of conversion to data loaded into result register

2tc(CO)

td(ADCINT)

Delay time, ADC flag to ADC interrupt

2tc(CO)

† The ADC timing diagram represents a typical conversion sequence. See the ADC chapter in the TMS320LF/LC240xA DSP Controllers Reference

Guide: System and Peripherals (literature number SPRU357) for more details.

‡ The total sample/hold and conversion time is determined by the summation of td(SOC-SH), tw(SH), tw(C), and td(EOC).

§ Can be varied by ACQ Prescaler bits in the ADCTRL1 register

tw(C)

tc(AD)

ADC Clock

Analog Input

Bit Converted

td(SOC−SH)

EOC/Convert

Internal Start/

Sample Hold

Start of Convert

XFR to RESULTn

tw(SHC)

td(EOC)

tw(SH)

td(ADCINT)

ADC Interrupt

Figure 51. Analog-to-Digital Internal Module Timing

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