TMS320LC2401AVFS datasheet(60/134 Pages) TI

60 / 134 page

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

clock domains

All 240xA-based devices have two clock domains:

1. CPU clock domain − consists of the clock for most of the CPU logic

2. System clock domain − consists of the peripheral clock (which is derived from CLKOUT of the CPU) and

the clock for the interrupt logic in the CPU.

When the CPU goes into IDLE mode, the CPU clock domain is stopped while the system clock domain continues

to run. This mode is also known as IDLE1 mode. The 240xA CPU also contains support for a second IDLE mode,

IDLE2. By asserting IDLE2 to the 240xA CPU, both the CPU clock domain and the system clock domain are

stopped, allowing further power savings. A third low-power mode, HALT mode, the deepest, is possible if the

oscillator and WDCLK are also shut down when in IDLE2 mode.

Two control bits, LPM1 and LPM0, specify which of the three possible low-power modes is entered when the

IDLE instruction is executed (see Table 11). These bits are located in the System Control and Status

System and Peripherals (literature number SPRU357).

Table 11. Low-Power Modes Summary

LOW-POWER MODE

LPMx BITS

SCSR1

[13:12]

CPU

CLOCK

DOMAIN

SYSTEM

CLOCK

DOMAIN

WDCLK

STATUS

PLL

STATUS

OSC

STATUS

FLASH

POWER

EXIT

CONDITION

CPU running normally

—

IDLE1 − (LPM0)

Off

Peripheral

Interrupt,

External Interrupt,

Reset,

PDPINTA/B

IDLE2 − (LPM1)

Off

Wakeup

Interrupts,

External Interrupt,

Reset,

PDPINTA/B

HALT − (LPM2)

[PLL/OSC power down]

Off

Off†

Reset,

PDPINTA/B

† The Flash must be powered down by the user code prior to entering LPM2. For more details, see the TMS320LF/LC240xA DSP Controllers

Reference Guide: System and Peripherals (literature number SPRU357).

other power-down options

240xA devices have clock-enable bits to the following on-chip peripherals: ADC, SCI, SPI, CAN, EVB, and EVA.

Clock to these peripherals are disabled after reset; thus, start-up power can be low for the device.

Depending on the application, these peripherals can be turned on/off to achieve low power.

See the SCSR1 register for details on the peripheral clock enable bits.

digital I/O and shared pin functions

The 240xA has up to 41 general-purpose, bidirectional, digital I/O (GPIO) pins—most of which are shared

between primary functions and I/O. Most I/O pins of the 240xA are shared with other functions. The digital I/O

ports module provides a flexible method for controlling both dedicated I/O and shared pin functions. All I/O and

shared pin functions are controlled using eight 16-bit registers. These registers are divided into two types:

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