TMS320LC2401AVFS datasheet(84/134 Pages) TI

84 / 134 page

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A

TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

low-power mode timing

switching characteristics over recommended operating conditions [H = 0.5tc(CO)]

(see Figure 30, Figure 31, and Figure 32)

PARAMETER

LOW-POWER MODES

MIN

TYP

MAX

UNIT

Delay time, CLKOUT switching to

IDLE1

LPM0

× tc(CO)

td(WAKE-A)

Delay time, CLKOUT switching to

program execution resume

IDLE2

LPM1

× tc(CO)

td(IDLE-COH)

Delay time, Idle instruction executed to

CLKOUT high

IDLE2

LPM1

4tc(CO)

td(WAKE-OSC)

Delay time, wakeup interrupt

asserted to oscillator running

HALT

LPM2

OSC start-up

time

td(IDLE-OSC)

Delay time, Idle instruction executed to

oscillator power off

HALT

{PLL/OSC power down}

LPM2

4tc(CO)

td(EX)

Delay time, reset vector executed after PLL lock time

36H

WAKE INT†

CLKOUT

A0−A15

td(WAKE−A)

† WAKE INT can be any valid interrupt or RESET.

Figure 30. IDLE1 Entry and Exit Timing − LPM0

td(WAKE−A)

td(IDLE−COH)

WAKE INT†

CLKOUT

A0−A15

† WAKE INT can be any valid interrupt or RESET.

Figure 31. IDLE2 Entry and Exit Timing − LPM1

td(EX)

td(IDLE−COH)

td(IDLE−OSC)

RESET

CLKOUT

A0−A15

td(WAKE−OSC)

tw(RSL)

Figure 32. HALT Mode − LPM2

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