TMS320LC2401AVFS datasheet(65/134 Pages) TI

65 / 134 page

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

generating wait states with the READY signal

When the READY signal is low, the LF2407A waits one CLKOUT cycle and then checks READY again. The

LF2407A does not continue executing until the READY signal is driven high; therefore, if the READY signal is

not used, it should be pulled high.

The READY pin can be used to generate any number of wait states. However, when the LF2407A operates at

full speed, it may not respond fast enough to provide a READY-based wait state for the first cycle. For extended

wait states using external READY logic, the on-chip wait-state generator should be programmed to generate

at least one wait state.

generating wait states with the LF2407A on-chip software wait-state generator

The software wait-state generator can be programmed to generate zero to seven wait states for a given off-chip

memory space (program, data, or I/O), regardless of the state of the READY signal. These zero to seven wait

states are controlled by the wait-state generator register (WSGR) (I/O FFFFh). For more detailed information

on the WSGR and associated bit functions, see the TMS320LF/LC240xA DSP Controllers Reference Guide:

System and Peripherals (literature number SPRU357).

watchdog (WD) timer module

The x240xA devices include a watchdog (WD) timer module. The WD function of this module monitors software

and hardware operation by generating a system reset if it is not periodically serviced by software by having the

correct key written. The WD timer operates independently of the CPU. It does not need any CPU initialization

to function. When a system reset occurs, the WD timer defaults to the fastest WD timer rate available (WDCLK

signal = CLKOUT/512). As soon as reset is released internally, the CPU starts executing code, and the WD timer

begins incrementing. This means that, to avoid a premature reset, WD setup should occur early in the power-up

sequence. See Figure 19 for a block diagram of the WD module. The WD module features include the following:

D WD Timer

−

Seven different WD overflow rates

−

A WD-reset key (WDKEY) register that clears the WD counter when a correct value is written, and

generates a system reset if an incorrect value is written to the register

−

WD check bits that initiate a system reset if an incorrect value is written to the WD control register

(WDCR)

D Automatic activation of the WD timer, once system reset is released

−

Three WD control registers located in control register frame beginning at address 7020h.

NOTE: All registers in this module are 8-bit registers. When a register is accessed, the register data is in the lower byte, the upper byte

is read as zeros. Writing to the upper byte has no effect.

Figure 19 shows the WD block diagram. Table 14 shows the different WD overflow (time-out) selections.

The watchdog can be disabled in software by writing ‘1’ to bit 6 of the WDCR register (WDCR.6) while bit 5 of

the SCSR2 register (SCSR2.5) is 1. If SCSR2.5 is 0, the watchdog will not be disabled. SCSR2.5 is equivalent

to the WDDIS pin of the TMS320F243/241 devices.

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