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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320LC2401AVFS датащи(PDF) 99 Page - Texas Instruments |
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TMS320LC2401AVFS датащи(HTML) 99 Page - Texas Instruments |
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99 / 134 page  TMS320LF2407A,TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145K − JULY 2000 − REVISED AUGUST 2005 99 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 external memory interface read timing switching characteristics over recommended operating conditions for an external memory interface read at 40 MHz [H = 0.5tc(CO)] (see Figure 45) PARAMETER MIN MAX UNIT td(COL-CNTL) Delay time, CLKOUT low to control valid 4 ns td(COL-CNTH) Delay time, CLKOUT low to control inactive 5 ns td(COL-A)RD Delay time, CLKOUT low to address valid 8 ns td(COH-RDL) Delay time, CLKOUT high to RD strobe active 5 ns td(COL-RDH) Delay time, CLKOUT low to RD strobe inactive high −8 1 ns td(COL-SL) Delay time, CLKOUT low to STRB strobe active low 5 ns td(COL-SH) Delay time, CLKOUT low to STRB strobe inactive high 6 ns td(WRN) Delay time, W/R going low to R/W rising 5 ns th(A)COL Hold time, address valid after CLKOUT low 2 ns tsu(A)RD Setup time, address valid before RD strobe active low H − 7 ns th(A)RD Hold time, address valid after RD strobe inactive high 0 ns timing requirements [H = 0.5tc(CO)] (see Figure 45) MIN MAX UNIT ta(A) Access time, read data from address valid 2H −10 ns ta(RD) Access time, read data from RD low H − 7 ns tsu(D)RD Setup time, read data before RD strobe inactive high 8 ns th(D)RD Hold time, read data after RD strobe inactive high 0 ns th(AIV-D) Hold time, read data after address invalid 0 ns |
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