MNSC140CORE datasheet(20/80 Pages) FREESCALE

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MSC8102 Quad Core Digital Signal Processor, Rev. 12

1-10

Freescale Semiconductor

Signals/Connections

1.5 Memory Controller Signals

Refer to the Memory Controller chapter in the MSC8102 Reference Manual for details on configuring these

signals.

NMI

Input

Non-Maskable Interrupt

When an external device asserts this line, it generates an non-maskable interrupt in the MSC8102, which is

processed internally (default) or is directed to an external host for processing (see NMI_OUT).

NMI_OUT

Output

Non-Maskable Interrupt Output

An open-drain pin driven from the MSC8102 internal interrupt controller. Assertion of this output indicates

that a non-maskable interrupt is pending in the MSC8102 internal interrupt controller, waiting to be handled

by an external host.

PSDVAL

Input/Output

Port Size Data Valid

Indicates that a data beat is valid on the data bus. The difference between the TA pin and the PSDVAL pin

is that the TA pin is asserted to indicate data transfer terminations, while the PSDVAL signal is asserted with

each data beat movement. When TA is asserted, PSDVAL is always asserted. However, when PSDVAL is

asserted, TA is not necessarily asserted. For example, if the DMA initiates a double word (2

× 64 bits)

transaction to a memory device with a 32-bit port size, PSDVAL is asserted three times without TA and,

finally, both pins are asserted to terminate the transfer.

IRQ7

INT_OUT

Input

Output

Interrupt Request 7

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Interrupt Output

Assertion of this output indicates that an unmasked interrupt is pending in the MSC8102 internal interrupt

controller.

Notes:

See the System Interface Unit (SIU) chapter in the

MSC8102 Reference Manual for details on how to configure these pins.

When used as the bus control arbiter, the MSC8102 can support up to three external bus masters. Each master uses its own

set of Bus Request, Bus Grant, and Data Bus Grant signals (BR/BG/DBG, EXT_BR2/EXT_BG2/EXT_DBG2, and

EXT_BR3/EXT_BG3/EXT_DBG3). Each of these signal sets must be configured to indicate whether the external master is or

is not a MSC8102 master device. See the Bus Configuration Register (BCR) description in the System Interface Unit (SIU)

chapter in the

MSC8102 Reference Manual for details on how to configure these pins. The second and third set of pins is

defined by EXT_xxx to indicate that they can only be used with external master devices. The first set of pins (BR/BG/DBG)

have a dual function. When the MSC8102 is not the bus arbiter, these signals (BR/BG/DBG) are used by the MSC8102 to

obtain master control of the bus.

Table 1-6.

Memory Controller Signals

Signal Name

Type

Description

BCTL0

Output

System Bus Buffer Control 0

Controls buffers on the data bus. Usually used with BCTL1. The exact function of this pin is defined

by the value of SIUMCR[BCTLC].

BCTL1

CS5

Output

System Bus Buffer Control 1

Controls buffers on the data bus. Usually used with BCTL0. The exact function of this pin is defined

by the value of SIUMCR[BCTLC].

System and Local Bus Chip Select 5

Enables specific memory devices or peripherals connected to MSC8102 buses.

BM[0–2]

TC[0–2]

BNKSEL[0–2]

Input

Input/Output

Output

Boot Mode 0–2

Defines the boot mode of the MSC8102. This signal is sampled on PORESET deassertion.

Transfer Code 0–2

The bus master drives these pins during the address tenure to specify the type of the code.

Bank Select 0–2

Selects the SDRAM bank when the MSC8102 is in 60x-compatible bus mode.

Table 1-5.

DSI, System Bus, and Interrupt Signals (Continued)

Signal Name

Type

Description

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